JPS54103664A - Digital counter - Google Patents

Digital counter

Info

Publication number
JPS54103664A
JPS54103664A JP1096278A JP1096278A JPS54103664A JP S54103664 A JPS54103664 A JP S54103664A JP 1096278 A JP1096278 A JP 1096278A JP 1096278 A JP1096278 A JP 1096278A JP S54103664 A JPS54103664 A JP S54103664A
Authority
JP
Japan
Prior art keywords
stage
gate
input terminal
circuit
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1096278A
Other languages
Japanese (ja)
Inventor
Hiroshi Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1096278A priority Critical patent/JPS54103664A/en
Publication of JPS54103664A publication Critical patent/JPS54103664A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To decrease greatly the number of the component element of each stage as well as to reduce the signal transmission delay of each stage by constituting the unit stage of the counter with the steering-gate circuit and the bistable circuit. CONSTITUTION:Stage 9 consists of bistable circuit 25 comprising NOR gate 7 and 8 which are cross-coupled each other and steering-gate circuit 26 comprising AND gate 5 and 6 one input terminal of which is connected in common and the other input terminal is connected to one input terminal of NOR gate 7 and 8. The output of circuit 26 is supplied to the input terminal of next stage 14. In such constitution, the trigger pulse row is applied to input terminal A, and thus the signal obtained by dividing the trigger pulse into two emerges at the output side of circuit 26 to be then supplied to next stage 14. And the signals obtained by dividing the input into two are delivered in sequence from each of the subsequent stages. In this way, the counter is constituted with just the gate of four units of the stage, so the signal transmission delay is reduced greatly to be used up to a high frequency.
JP1096278A 1978-02-01 1978-02-01 Digital counter Pending JPS54103664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1096278A JPS54103664A (en) 1978-02-01 1978-02-01 Digital counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1096278A JPS54103664A (en) 1978-02-01 1978-02-01 Digital counter

Publications (1)

Publication Number Publication Date
JPS54103664A true JPS54103664A (en) 1979-08-15

Family

ID=11764793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1096278A Pending JPS54103664A (en) 1978-02-01 1978-02-01 Digital counter

Country Status (1)

Country Link
JP (1) JPS54103664A (en)

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