JPS573419A - Phase comparator - Google Patents
Phase comparatorInfo
- Publication number
- JPS573419A JPS573419A JP7687280A JP7687280A JPS573419A JP S573419 A JPS573419 A JP S573419A JP 7687280 A JP7687280 A JP 7687280A JP 7687280 A JP7687280 A JP 7687280A JP S573419 A JPS573419 A JP S573419A
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase
- lead
- nand
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To make unnecessary a kick-off circuit for PLL in burst operation, by taking the phase characteristics of a phase comparator as saw-tooth shape and taking the average value of an output voltage as a middle value of high and low level. CONSTITUTION:An NAND 8 is operated as a phase comparator having a triangle phase characteristics. A D-FF9 detects the phase lag and lead of an input signal, and it is at low level when the phase of an input Y is lead to that of an input X and at high level when lagged. Thus, when an output Z of an EX-OR1 is lead, the output of the NAND gate 8 is outputted as it is, and when lagged, it is inverted. Thus, the output Z causes a saw tooth wave characteristics. Further, one of the inputs X, Y is fixed and a signal of 50% duty is inputted to another, the output of the NAND 8 has 50% duty and the average voltage is at the middle of high and low levels.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7687280A JPS573419A (en) | 1980-06-06 | 1980-06-06 | Phase comparator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7687280A JPS573419A (en) | 1980-06-06 | 1980-06-06 | Phase comparator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS573419A true JPS573419A (en) | 1982-01-08 |
Family
ID=13617721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7687280A Pending JPS573419A (en) | 1980-06-06 | 1980-06-06 | Phase comparator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS573419A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58129622A (en) * | 1982-01-22 | 1983-08-02 | ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング | Syncronizer for clock control type data processor |
JPH0322436U (en) * | 1989-07-17 | 1991-03-07 |
-
1980
- 1980-06-06 JP JP7687280A patent/JPS573419A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58129622A (en) * | 1982-01-22 | 1983-08-02 | ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング | Syncronizer for clock control type data processor |
JPH0322436U (en) * | 1989-07-17 | 1991-03-07 |
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