JPS5527776A - Programmable counter circuit - Google Patents
Programmable counter circuitInfo
- Publication number
- JPS5527776A JPS5527776A JP10112178A JP10112178A JPS5527776A JP S5527776 A JPS5527776 A JP S5527776A JP 10112178 A JP10112178 A JP 10112178A JP 10112178 A JP10112178 A JP 10112178A JP S5527776 A JPS5527776 A JP S5527776A
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- output
- terminal
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
Landscapes
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To enable the input control of the counter to the input signal of high frequency by controlling the input state of the delay circuit via the output of the delay circuit, thus eliminating the malfunction to the high frequency input. CONSTITUTION:Divider circuits 1-4 connected vertically are provided with the count input sent from terminal 61 used as the input, and the output of terminals 21, 23 and 24 among output terminals 21-24 plus input terminals 11-14 of circuits 1-4 are supplied to input terminal 17 of delay circuit 71 via NOR circuit 41. At the same time, circuits 1-4 are controlled by the output of set/reset switch circuit 51, and the count input is supplied to clock input terminal 47 of circuit 71. And circuit 71 is actuated by the initial count input. Then the output from output terminal 27 of circuit 71 is applied to circuit 51 and 41 to control the input state of circuit 71. As a result, the normal control is given to circuit 71 against the high frequency input signal, thus preventing occurrence of the malfunction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10112178A JPS5527776A (en) | 1978-08-18 | 1978-08-18 | Programmable counter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10112178A JPS5527776A (en) | 1978-08-18 | 1978-08-18 | Programmable counter circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5527776A true JPS5527776A (en) | 1980-02-28 |
JPS6144415B2 JPS6144415B2 (en) | 1986-10-02 |
Family
ID=14292235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10112178A Granted JPS5527776A (en) | 1978-08-18 | 1978-08-18 | Programmable counter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5527776A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100355302B1 (en) * | 2000-03-14 | 2002-10-11 | 학교법인 포항공과대학교 | Programmable frequency divider by high speed counter |
-
1978
- 1978-08-18 JP JP10112178A patent/JPS5527776A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100355302B1 (en) * | 2000-03-14 | 2002-10-11 | 학교법인 포항공과대학교 | Programmable frequency divider by high speed counter |
Also Published As
Publication number | Publication date |
---|---|
JPS6144415B2 (en) | 1986-10-02 |
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