JPS564932A - Tristate circuit - Google Patents
Tristate circuitInfo
- Publication number
- JPS564932A JPS564932A JP7919079A JP7919079A JPS564932A JP S564932 A JPS564932 A JP S564932A JP 7919079 A JP7919079 A JP 7919079A JP 7919079 A JP7919079 A JP 7919079A JP S564932 A JPS564932 A JP S564932A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- signal
- gate
- held
- potential point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce circuit elements in number by connecting two MOSFETs of the 1st conduction type in series between the 1st potential point and an output terminal, by further connecting MOSFET of the 2nd conduction type between the output terminal and the 2nd potential point, and by combining them with an NOR circuit. CONSTITUTION:Between the 1st potential point -Vdd and output terminal T0, N-type MOSFETQ1, Q2 are connected in series and between terminal T0 and the 2nd potential point GND, P-type MOSFETQ3 is also connected. The 1st input terminal T1 is connected to one input of NOR gate G1, the 2nd input terminal T2 is connected to the gate of FETQ1 and the other input of gate G1, and the output of gate G1 is led to the gates of FETQ2, Q3. Assuming that signal V2 at terminal T2 is held at ''0'' and signal V1 at terminal T1 is at ''1'', signal V0 at terminal T0 is held at ''1'' and assuming signals V2 and V1 to be held at ''0'' obtains signal V0 of ''0''. When signals V1 and V2 are considered to be held at ''1'' or when signals V2 and V1 are at ''1'' and ''0'' respectively, signal V0 maintains a floating level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7919079A JPS564932A (en) | 1979-06-25 | 1979-06-25 | Tristate circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7919079A JPS564932A (en) | 1979-06-25 | 1979-06-25 | Tristate circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS564932A true JPS564932A (en) | 1981-01-19 |
Family
ID=13683049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7919079A Pending JPS564932A (en) | 1979-06-25 | 1979-06-25 | Tristate circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS564932A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0102670A2 (en) * | 1982-09-03 | 1984-03-14 | Lsi Logic Corporation | Tri-state circuit element |
JPS6072319A (en) * | 1983-09-28 | 1985-04-24 | Nec Ic Microcomput Syst Ltd | Integrated circuit |
JPS6125326A (en) * | 1984-07-16 | 1986-02-04 | Nec Corp | Buffer circuit |
EP0547525A1 (en) * | 1991-12-18 | 1993-06-23 | Siemens Aktiengesellschaft | CMOS driver stage |
-
1979
- 1979-06-25 JP JP7919079A patent/JPS564932A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0102670A2 (en) * | 1982-09-03 | 1984-03-14 | Lsi Logic Corporation | Tri-state circuit element |
EP0102670A3 (en) * | 1982-09-03 | 1984-07-04 | Lsi Logic Corporation | Tri-state circuit element |
JPS6072319A (en) * | 1983-09-28 | 1985-04-24 | Nec Ic Microcomput Syst Ltd | Integrated circuit |
JPH0430764B2 (en) * | 1983-09-28 | 1992-05-22 | ||
JPS6125326A (en) * | 1984-07-16 | 1986-02-04 | Nec Corp | Buffer circuit |
EP0547525A1 (en) * | 1991-12-18 | 1993-06-23 | Siemens Aktiengesellschaft | CMOS driver stage |
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