JPS6125326A - Buffer circuit - Google Patents

Abstract

PURPOSE:To decrease the number of transistors (TRs) of a buffer circuit using an output control signal to apply high impedance control and to reduce the occupied area by providing a gate circuit inputting the output control signal and a data input signal to the buffer circuit. CONSTITUTION:A data input signal DIN is fed to an inverter 31 of a buffer circuit having an inverted output, an output of the inverter 31 and an output control signal OUT are inputted to a 2-input NAND gate 32 and an output of the gate 32 is fed to a gate of a transistor (TR)32 of a P-channel output driver. Further, the control signal OUT is fed to a gate of an N-channel cut-off TR35 and the input signal DIN is fed to a gate of a TR36 of an N-channel output driver. The TRs 34-36 are connected between a power potential 33 and a common potential 37 and a connecting point between the TR34 and TR35 is connected to an output terminal DOUT. Then the number of operating TRs is decreased and the occupied area is reduced. Further, an inverter and a 2-input NAND gate are employed for the synchronous type buffer circuit of and a degree of freedom is given to the circuit design.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a buffer circuit that can perform high inlay control and is used on two sides, such as a pass circuit of a large-scale integrated circuit (hereinafter referred to as LSI) having a CMO8 structure.

[Prior art]

LSIs such as microcomputers have internal paths such as address buses and data buses for sending and receiving data, but since these internal paths are spread over a wide area within the LSI chip, their wiring capacity and wiring resistance increases. For this reason, a path buffer circuit is usually used when driving an internal path. Conventionally, a buffer circuit as shown in FIG. 1 or 2 has been used as such a pass buffer circuit, and this will be briefly explained with reference to the drawings.

In FIGS. 1 and 2, DIN indicates a data input signal, and DIN indicates a data output terminal to a path or the like. Both circuits shown in the figures are anti-phase buffers in which the data input signal Dr is inverted and outputted to the output terminal Doυ. O
UT is an output control signal, and when this signal goes to "H" level, the data input signal D! The inverted data of is output to the output terminal DOυD, and when it becomes 'L'' level, the data output terminal Doo
Ding becomes a high impedance state. As for the output control method, in the circuit shown in FIG. 1, the output drivers 15 and 16 are controlled by the two control gates (two-way NAND gate 12 and two-way NOR gate 16).In addition, in the circuit shown in FIG. Transistors 24 and 25 and output drivers 26 and 26 are connected in series to output the output control signal OU.
It is controlled by T.

In the buffer circuit shown in Figure 1, the output driver 1
Two-man NA as a control gate to control the outputs of 5 and 16
It requires an ND gate 12 and a two-manufactured NOR gate 16, and has the drawback that the number of transistors is larger than in the buffer circuit shown in FIG. 2, resulting in a slower speed.

On the other hand, in the buffer circuit shown in Figure 2, the output driver 26°26
and cut-off transistors 24 and 25 are connected in series, so if the same transistors as the output drivers 15 and 16 in Figure 1 are used, the drive capability will be IA compared to the buffer circuit in Figure 1. Therefore,' !In order to make the buffer circuit shown in Figure J2 have the same drive capability as the circuit shown in Figure 1, it is necessary to double the gate width (hereinafter referred to as W) of each transistor. Since the ratio of the mutual conductance (hereinafter referred to as gm) of the P-channel transistor to the gm of the P-channel transistor is approximately 2:1, the "H" level side (P-channel drive) and the "L" level side
In order to equalize each drive capability on the level side (N?Yanel drive), it is necessary to set the ratio of W of the P-channel transistor and the N-channel transistor to 2=1.

Therefore, the area of the buffer circuit shown in FIG. 1 will be compared with the area of the buffer circuit shown in FIG. 2 while taking into consideration the ratio of W. In order to simplify the calculation, it is assumed that the transistor width is the same for all the transistors in FIGS. 1 and 2, and only W is compared. The gate width/gate length (hereinafter referred to as W/L) of the N-channel driver 16 in the circuit of FIG. 1 is 50''/l.
If θ”1, the W/L of the P channel driver 15 is Z
oo /10 will be required. In addition, in the circuit of FIG. 2, the N-channel driver 26 and the cutoff transistor 25 are both (2 W
/L.

= 1001i''/10'', and both the P channel driver 26 and the cutoff transistor 24 (2W/L
=200"'/10"1 is required. Also, the inverter 11.18 in FIG. 1 and the inverter 21 in FIG.
It consists of f-channel transistor 46, and the size of each transistor is P'f-channel transistor 42, W/L.
= 20'1''/1OIJ''', then N channel transi: x 943 power W/L = 1o'''/1o'-
"C' W (D sum = 30 Dr''. Furthermore, as shown in FIG. 5, the two-man NAND 12 connects P-channel transistors 52 and 56 in parallel, and connects N-channel transistors 54 and 55 in series. The size of each of the P-channel transistor 52.56 and the N-channel transistor 54.55 is W/L=20"A10"24, and the sum of W is 80"1.2Manual powerN .

R13 is composed of P-channel transistors 62 and 63 connected in series and N-channel transistors 64 and 65 connected in parallel, as shown in FIG. Since the channel driver 16 has a small W, the size of the transistors 62 to 65 can be small, and the P channel transistors 62 and 63
are respectively W/L = 20"/1o11m, and N-channel transistors 64°65 are each W/L = 10""
/10'-, the sum of W is 60"1.

Therefore, the W design of the buffer circuit in Figure 1 is as follows: Inverter 11.18 (60") and two-man NAND 12 (80")
”) 82 human power NOR13 (60”) Totora (Ha15
．． 16 (150'rn) (D each W'r: Kaete Ws
-350"1. On the other hand, the sum W2 of the buffer circuit in FIG. Therefore, the area of the buffer circuit in FIG. 2 is 1.8 compared to the buffer circuit in FIG. 1.
It has the disadvantage of being twice as large.

As described above, conventional buffer circuits have drawbacks such as an increase in the number of transistors as in the circuit shown in FIG. 1, and an increase in area as in the circuit in FIG.

Also, the circuits in Figures 1 and 2 are anti-phase buffers, but these are in-phase buffers (2). It is necessary to add an inverter to create an inverted signal of the signal DXN, and since the number of transistors is different between in-phase and anti-phase, care must be taken when designing the circuit.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks, provide a buffer circuit that occupies a small area, uses a small number of transistors, and has a high degree of freedom in circuit design.

[Structure of the invention]

The present invention (: such a buffer circuit has a gate circuit that inputs an output control signal and a data input signal, and connects the output of the gate circuit to a source electrode of a gate transistor of a first transistor to a first potential, The second transistor and the third transistor are connected in series, one electrode of the series-connected transistor is connected to a second potential (2), and the other electrode is connected to the drain electrode of the first transistor. It is characterized by being connected to the output terminal.

[Explanation of Examples]

Examples of the present invention will be described below. FIG. 6 is a circuit diagram of a buffer circuit according to an embodiment of the present invention (1).
In the figure, Dry is a data input signal, OUT is an output control signal, and DOUT is an output terminal of the buffer circuit, which is connected to an internal path line and the like. 61 is an inverter that receives the data input signal D! Outputs an inverted signal. 62 is a two-man NAND gate that receives the output signal of the inverter 61 and the output control signal OUT, 66 is a power supply potential, 64 is a P-channel output driver, 65 is a Ny-Yannel cutoff transistor, and 66 is an Nf-Yannel output driver. It is.

The operation of the circuit shown in Figure 9J6 will be explained.

First, when the output control signal OUT is at the "L" level, the N-channel cutoff transistor 65 is turned off and the two-manufactured NAND gate 62 outputs the "H" level.
Channel output driver 34 is also turned off. Therefore, the output terminal Doυ is in a high impedance state (=) regardless of the data input signal DIN.

When the output control signal OUT is at "H" level, the N-channel cutoff transistor 65 is turned on. If the data human power signal DI)l is at the "■I" level, the inverter 61 outputs the "L11 level", so the two manual power NANI)
52 outputs H” level and connects the Py-Yanel output driver 6.
4 is turned off, but the N-channel output driver 66 is turned on, and the output terminal DoIJrl2 outputs the ground potential, that is, the IIL11 level. However, the data input signal DxH is “
If it is L I+ level, N channel output driver 66
is turned off, but the inverter 61 outputs the "H" level and the two-man power NAND 32 outputs the "L" level, so the P channel output driver 64 is turned on and the output terminal Douy-= outputs the power supply potential, that is, the "H" level. Ru.

In this way, when the output control signal OUT is at the "H" level, the output terminal Douy4 outputs a signal with the opposite phase to the data input signal D!, and when the output control signal OUT is at the "L" level, the output terminal Douy4 is in a high impedance state (= Become.

C2 In order to make the drive capability of the output driver of the circuit in FIG. 6 equivalent to the drive capability of the buffer circuit (=) in FIG. 1, the size of the output driver is as follows.

First, the P channel driver 64 may have the same W/L = 100 /lo as the Pf channel driver 15 in FIG.

N-channel driver 66 and cutoff transistor 65
is the N-channel driver 26. of FIG. Similarly to the cut-off transistor 25, the N-channel driver 1 in FIG.
All you need to have is W/L Q that is twice that of 6 < W/L = 100
/10.

Let us now compare the area occupied by each circuit in FIGS. 1 and 2 with the area occupied by the circuit of the embodiment shown in FIG. 6. The sum Ws of W in the circuit of the embodiment is the inverter 61 (30"rn)
and 2-man power NAND62 (801m) and driver 64,
Add each W of 35 and 36 (3oo”1) and get Ws =
410"", Wl of the conventional example is 350", W2 is 6
30"1, so if we ratio these by C2, Wl:
Wx: Ws = 1: 1.8:
1.17, and the area of the circuit of the embodiment is a little larger than the buffer circuit of FIG. 1, but can be much smaller than the buffer circuit of FIG.

Next, a comparison will be made between the circuit of the embodiment and the circuit of the conventional example regarding the number of transistors used. Here, the inverter has two transistors and a two-power NAND as shown in Figure 4.
and two-person NOR are shown in Figures 5 and 6, respectively (
: Requires 4 transistors. Table 1 shows the number of transistors used in each circuit shown in Figures 1 and 2.
and are listed in Table 2. Note that Figure 1 and Figure 2 are both circuit diagrams of anti-phase buffer circuits, but the number of transistors used when making them into in-phase buffer circuits is also shown in each table (2). Also, in each table, the numbers in parentheses are The numbers of each element in each figure are shown, and D!N indicates an inverter for inverting the data input signal DIN, although not shown.

Table 1 Now, the embodiment shown in FIG. 6 is an anti-phase buffer circuit, but an embodiment of an in-phase buffer circuit according to the present invention is shown in FIG. 9s7. 71 is an inverter, 72 is a two-man NAND gate,
74, 75, and 76 are P channel output drivers, respectively.
There is an N-channel cutoff transistor and an Nf-channel output driver, and the transistors used are exactly the same as the transistors in the anti-phase buffer circuit of FIG. Table 6 shows the number of transistors used in each circuit shown in FIG. 6 and the seventh factor.

Table 6 In the circuit shown in FIG. 1 or 2, the number of transistors used for the in-phase buffer and the anti-phase buffer is different, so the above results are summarized by taking the average. Taking the ratio of the number of transistors used in each circuit shown in Figures 1, 2, and 6, T+, Tz, and Ts, Tr: Tx: Ts = 13: 7: 9 = 1.86
: 1 : 1.29, and the number of transistors in the circuit of the example is slightly larger than that of the buffer circuit in FIG.
It can be made much smaller than the buffer circuit shown in the figure.

In order to compare the area occupied by each of the circuits mentioned above and the number of transistors used in each circuit, multiplying the ratios of the two together, we get Ws・Tt : Wt・Tx : Wm・Ts=1.
23:1.19:1, and it can be seen that the buffer circuit according to the example (=) has a smaller area and fewer transistors than the conventional buffer circuit.

Furthermore, in the circuit according to the present invention, there is an anti-phase buffer (Fig. 6).
Since the number of transistors used in the in-phase buffer and the in-phase buffer (FIG. 7) are the same, there is also the advantage that the degree of freedom in circuit design is increased.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to realize a buffer circuit that can perform high impedance control with a smaller number of transistors and a smaller area than conventional circuits, and also has great effects such as increasing the degree of freedom in circuit design.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a conventional buffer circuit, FIG. 6 is a circuit diagram of a buffer circuit with negative phase output according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of an inverter. , fs5
The figure is a circuit diagram of a two-manpower NAND, FIG. 6 is a circuit diagram of a two-manpower NOR, and FIG. 7 is a circuit diagram of an in-phase output buffer circuit according to another embodiment (1) of the present invention. Input signal Door...Data output terminal OUT...Output control signal I, I+, It...Input 0...Output 11, 18.21.61.71...Inverter 12,
62.72...2-manpower NAND gate 16...2-manpower NOR gate 1.22, 33, 41, 51.61.76...Power supply potential 17, 27.37.44.56.66, 77. ...Earth 15.16.25~26.54~36,42,
45.52~55°62~65.74~76...Transistor. Patent applicant: NEC Corporation゛・～21〕・Figure 3

Claims (1)

[Claims] A buffer circuit that performs high impedance control using an output control signal, comprising a gate circuit that inputs the output control signal and the data input signal, and an output of the gate circuit is connected to the gate electrode of the first transistor. connecting the data input signal to a gate electrode of a second transistor, connecting the output control signal to a gate electrode of a third transistor, and connecting the data input signal to a gate electrode of a third transistor;
connecting a source electrode of a transistor to a first potential, connecting the second transistor and the third transistor in series, and connecting one electrode of the series-connected transistor to a second potential; A buffer circuit characterized in that the other electrode is connected to the drain electrode of the first transistor to serve as an output terminal.