JPH03291016A - Logic circuit - Google Patents

Abstract

PURPOSE:To provide a NOT input to a required input terminal without increasing the number of transistor(TRs) by forming a logic circuit of the channels of 1st-4th TRs while containing channels different in conductivity type, and providing NOT function to TR pairs themselves of channels different in conductivity type in these TRs. CONSTITUTION:Each of input terminals A-D is provided with a C-MOS TR pair whose gates are connected in common, and either a P-channel TR or an N-channel TR is turned on with respect to an input signal whose level is 'H' or 'L'. When an 'L' level input signal is supplied to all the input terminals A-D, P-channel TRs Q1-Q4 are turned on and N-channel TRs Q5-Q8 are turned off. Thus, a high level 'H' from a high level power supply line 1 is outputted to an output terminal O via the TRs Q1, Q2. Moreover, when an 'H' level input signal is supplied to all the input terminals A-D, P-channel TRs Q1-Q4 are turned off and N-channel TRs Q5-Q8 are turned on. Thus, a potential 'L' of a low potential power supply line 1 is outputted to the output terminal O via the TRs Q7, Q8.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the MO3 logic circuit, we have developed a logic circuit in which an AND-OR invert gate circuit having a negative input is configured with the same number of transistors as a conventional AND-OR invert gate circuit. For the purpose of providing this invention, a configuration is adopted in which the arrangement of transistor pairs connected to the input terminals of a conventional AND-OR invert gate circuit is swapped.

[Industrial application field]

The present invention relates to an improvement in a logic circuit composed of a plurality of transistors.

In recent years, semiconductor integrated circuits have become increasingly highly integrated.

Along with this, logic circuits formed within semiconductor chips (for example, basic OR, AND, NOT circuits, or logic circuits that combine these) are configured with fewer transistors to obtain the necessary logic. It is hoped that this will be done.

[Conventional technology]

Conventionally, MO3 logic circuits include composite gate circuits that are circuits that apply NAND circuits and NOR circuits.

One of them is an AND-OR invert gate circuit having a logic configuration as shown in FIGS. 3(a) and 3(b). This AND-OR invert circuit is shown in Figure 3 (
Input end E as shown in a).

It also consists of AND circuits 13 and 14 that take the logical product of signals input from the input terminals G and H, and a NOR circuit 15 that takes the negative logical sum of their outputs. -F + GH logic outputs.

This AND-OR invert gate circuit is shown in FIG.
), and its configuration is such that for each input terminal E, F, G, H, the gates of the P-channel type MO3) transistor and the N-channel type MOS transistor are common. are connected (for example, a pair of Ql1 and Ql7 to input terminal G).

And P channel type MOS transistor Qll-Ql
4 is connected between the high potential power supply line II and the output terminal 0, and the N-channel type MO3) transistors Q15 to Q1B are connected between the low potential power supply line 2 and the output terminal O.

By the way, by using the above-mentioned AND-OR invert gate circuit, as shown in FIG. 0 = E-3 + G-3 may be configured. In this case, conventionally, for example, A
The NOT circuit 16 is simply inserted into the control signal input to the ND circuit 14. In other words, this logic circuit has the fourth
When configured using the AND-OR invert gate circuit shown in the figure, a C-MOS inverter circuit 3 (Q19, Q20) is connected between the control terminal S and the input terminal F as shown in FIG.
The structure is set up.

[Problem to be solved by the invention]

However, as semiconductor integrated circuits become more highly integrated, it is desired that logic circuits be configured with a smaller number of transistors, but conventionally, as shown in FIG.
When giving a negative input to one of G and H, connect C to that input terminal.
- A new MOS impark circuit 3 (inversion circuit) was added. In other words, the MO3I-transistor is as shown in Fig. 3(a).
Two additional gates were required compared to the AND-OR invert gate circuit. Considering that this is a logic circuit, a considerable number of extra elements are required within the semiconductor integrated circuit.

Therefore, in the present invention, the AND-
With the same number of transistors as the OR invert gate circuit,
Another object of the present invention is to provide a logic circuit that can obtain the same logic as the AND-OR invert gate circuit shown in FIG. 4(a).

[Means to solve the problem]

FIG. 1 shows a circuit diagram of the principle of the present invention. In the figure, Ql-Q4
is a P-channel type MOS transistor, Q5 to Q8 are N-channel type MOS transistors, and X is a connection point. Note that the same parts as in FIG. 4 are given the same reference numerals.

The above object is to provide a logic circuit of the present invention with a high potential power supply line (V
CC), and the other terminal is commonly connected to the connection point (X). A third transistor having one terminal commonly connected to the second transistor (Q1, Q2) and the connection point (X), and the other terminal commonly connected to the output terminal (O). The fourth transistor (Q
3. Q4), the output terminal (O) and the low potential power line (VS
S) connected in series between the fifth. A sixth transistor (Q5, Q6) and a seventh transistor connected in parallel with the third circuit and in series between the output terminal (O) and the low potential power supply line (VSS). 8 transistors (Q1
, Q8), and the first. The second transistor (Q
1, Q2) and the above 5. The sixth transistor (Q5.Q
6), the gates are connected in pairs, and the third. Fourth
transistors (Q1, Q2) and the seventh transistor. The gates of the eighth transistors (Q5, Q6) are connected in a pair, and the pair of transistors whose gates are connected in a pair are both configured with channels of different conductivity types, and the first...
Second. Third. This is achieved in that the channels of the fourth transistor include channels of different conductivity types.

[Effect]

In the logic circuit of the present invention, in the configuration as described above, the first
．． Second. Third. A channel of the fourth transistor is configured to include channels of different conductivity types. As a result, the first. Second. Third. Since the pair of channel transistors of different conductivity types in the fourth transistor itself has a negation function, a negation input can be given to the required input terminal without increasing the number of transistors.

〔Example〕

The present invention will be explained in detail with reference to FIG.

FIG. 1 is an example of a circuit in which one input terminal A of an AND-OR invert gate circuit has a negative function.
In the AND-OR invert gate circuit shown in the figure, a P-channel type MOS transistor Q13 and an N-channel type MO3) transistor Q15 have their gates connected to the input terminal.
The positions of are switched. Therefore, that P,
The N-channel MOS transistor operates in the opposite manner to the input terminal E of a conventional AND-OR invert gate circuit with respect to the input signal input to the input terminal A, so the input terminal A is an input terminal to which a negative signal is input. Become.

The operation of the AND-OR invert gate circuit shown in FIG. 1 will be explained below.

In this circuit, the transistor pairs whose gates are commonly connected to the input terminals A, B, C, and D are respectively C-MO
Since it has 3 configurations, P and N channel type MO3)
Either one of the transistors is the input signal, ■]” or “L”
It becomes a turn-on against.

Now, when "°L" is input to all input terminals A, B, C, and D, P-channel type MOS transistors Q1 to Q4 are turned on, and N-channel type MOS transistors Q5 to Q4 are turned on.
Q8 is turned off. Therefore, the potential "H" of the high potential power supply line 1 is outputted to the pressure end O via the P-channel MO3) transistors Q1 and Q2.On the other hand, the input ends A, B,
When "H" is input to both C and D, P-channel type MO transistors Q1 to Q4 are turned off, N-channel type MOS transistors Q5 to Q8 are turned on, and an N-channel type MOS transistor is input to output terminal O. transistor Q7
．． The potential 11L' of the low potential power supply line 1 is outputted via Q8.゛L” and ’°H” at input terminals A, B, C, and D, respectively.
If N HI+2 “L”° is input,
Transistor Q2. Q3. Q6゜Ql is turned on, transistors Q1, Q4 . Q5 and Q8 are turned off, and transistors Q3. The potential ``L'' of the low potential power supply line 1 is outputted via Q6.

The truth table of the AND-OR invert gate circuit shown in FIG. 1 is shown in Table 1 below. Here, "0°" is "L", "1" is "H", A, B.

C and D indicate input ends, and 0 indicates an output end.

(Leaving space below) Table 1 In this way, the AND-OR invert gate circuit shown in Figure 1 allows the input signal to be input to the input terminal as logic 0 = A-B + CD without increasing the number of transistors. It becomes possible to give a negative input.

Next, a logic circuit showing the same logic as the conventional AND-OR invert gate circuit of FIG. 5 will be explained using FIGS. 2(a) and 2(b). FIG. 2(a) shows the AND circuit 10
, an ANDR circuit 11 whose one input is a negative input, and the negative input and one input terminal of the AND circuit 10 (input terminal A in this case).

It consists of a control terminal S commonly connected to C) and a NOR circuit whose inputs are the outputs of two AND circuits io and il, and shows the same logic as in FIG. 4(a).

The specific circuit configuration is as shown in FIG. 2(b), the input terminal A of the AND-OR invert gate circuit in FIG.
C is commonly connected, and it is used as a control terminal S. Therefore, in Table 1 above, this logic circuit has A=
Since it is the same as the part in C, the explanation of the operation will be omitted.

As described above, in this embodiment, the AND-
Since it is possible to show the same logic as the logic AND-ORN note gate circuit of FIG. 4 with the same eight transistors as the OR in-heart gate circuit, there is no need to use extra transistors.

In the above-described embodiment, the negative input is limited to the input terminal A, but it is clear that any input terminal B, C, or D other than the input terminal A may be used. Further, there may be two negative inputs, such as input terminals A and B, for example.

[Effects of the Invention] As explained above, in the logic circuit of the present invention, AND-
Even if an OR invert gate circuit has a negative input, it can be configured with the same number of transistors as a conventional AND-OR invert gate circuit, making a great contribution to higher integration of semiconductor integrated circuits.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the principle of the present invention, Figure 2 (a) is a diagram of an embodiment of a logic circuit, Figure 2 (b) is a specific circuit diagram of Figure 2 (a), and Figure 3 ( a) is a logic circuit diagram of a conventional AND-OR invert gate circuit, FIG. 3(b) is a conventional AND-OR invert gate circuit diagram, and FIG. 4(a) is a conventional ANDOR invert gate circuit with a negative input. FIG. 4(b) is a circuit diagram of a conventional AND-OR invert gate having a negative input. In the figure, 1 is a high potential power line (VCC), 2 is a low potential power line (VSS), 3 is a C-MOS inverter circuit (NOT circuit), 10, 13, 14 are AND circuits, and 11 is one input AND circuit that is negative human power, 12.15 is NO
R circuit, 16 is a negative circuit, Ql-Q4. Ql 1-Ql
4 is a P-channel type MOS transistor, Q5 to QB,
Q15 to Q18 are N-channel type MO3) transistors, A
-H indicates an input terminal, S indicates a control terminal, 0 indicates an output terminal, and X indicates a connection point. A〈45th day of the 7th month of the 7th day of the month A'' Tozukyu t E (CL) Sansho Ming's one side - ai'l 已 system 2. Group (α) Cb) I sister 0, ND-θR4) Bar L game FLU Lite No.

Claims (1)

[Claims] First and second transistors (Q1, Q2) and a third terminal having one terminal commonly connected to the connection point (X) and the other terminal commonly connected to the output terminal (O);
A fourth transistor (Q3, Q4), and fifth and sixth transistors (Q5, Q6) connected in series between the output terminal (O) and the low potential power supply line (VSS).
), connected in parallel with the third circuit and connected to the output terminal (O
) and a low potential power supply line (VSS), the first and second transistors (Q1, Q2) and the The gates of the fifth and sixth transistors (Q5, Q6) are connected as a pair, and the gates of the fifth and sixth transistors (Q5, Q6) are connected as a pair.
1, Q2) and the seventh and eighth transistors (Q5, Q
6) means that the gates are connected in pairs, and the transistor pairs to which the gates are connected in pairs are both configured with channels of different conductivity types, and the first, second, third, and fourth transistors A logic circuit comprising channels of different conductivity types.