JPH02232577A - Output circuit - Google Patents

Abstract

PURPOSE:To enable fast operation with a reduction in the number of elements by building a circuit having a diver control circuit, two compound gates and an output means. CONSTITUTION:This circuit is made up of a driver control circuit 10 comprising two input NANDs, two compound gates 21 and 22, an inverter 23, and an output drive circuit 20 comprising PMOS and NMOS transistors Tr 24 and 25. Then, at a normal mode, the circuit 10 outputs a tristate control signal DOE by inversion and two gates 21 and 22 also output output signals by inversion separately. According to the signals, any one state of a high level HL, a low level LL and a high impedance HI is outputted. At a test mode, the circuit 10 outputs a HL state, the gate 21 a LH state and the gate 22 a HL state separately. An output means outputs any one of the HL, LL and HI according to the states of test control signals Q, R and S. A circuit thus arranged allows a very small number of elements-- 18 of transistors -- and an output signal Din only passes through a double stage gate thereby enabling fast operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit for a semiconductor integrated circuit, and more particularly to an output circuit having a function of facilitating DC testing.

[Prior Art] Generally, a semiconductor integrated circuit has input circuits connected to each other,
It consists of an internal logic circuit and an output circuit.

To test this semiconductor integrated circuit, check the logic function of the internal logic circuit a! There are performance tests, DC tests, etc. The functional test is performed at the operating frequency of the semiconductor integrated circuit (1 to 5
This is done by applying a clock signal of a frequency close to the operating frequency (0 MHz) or a frequency close to the operating frequency to the semiconductor integrated circuit. Also, in the DC test, for example, the output of the output circuit is at a low level rLJ.
The logic level of the human input signal to the output circuit and the state of the internal logic circuit are set so that This is a test to determine.

Since the DC test requires a completely separate procedure to newly set the state of the internal logic circuit, it is performed separately from the functional test.

Note that the DC test is performed for each output circuit due to limitations of the equipment being tested, and several votes are required for testing one output circuit.
It takes a certain degree.

Nowadays, internal logic circuits have become highly integrated and complex, so that the output circuit outputs logic levels for testing, such as high level "H", low level rLJ, high impedance rZJ, etc. Many clock signals and complicated procedures are required to set the state of the .

As a result, the time required for the DC test becomes extremely long. Because of this, output circuits have been proposed that allow the output circuit to be set to any logic level regardless of the state of the internal logic lows.

FIG. 2 is a circuit diagram of an output circuit described in Japanese Unexamined Patent Publication No. 82-2B94.18. This output circuit is composed of a selection circuit 40, an output driver control circuit 50, and an output drive circuit 60.

The selection circuit 40 is composed of tri-state inverters 41, 42 and an inverter 43, and receives a test control signal T. Under one control, either one of the output signal (hereinafter simply referred to as output signal) "In" and the test-dedicated output signal TD1n from the internal logic circuit (not shown) is output. The selection circuit 40 outputs the test control signal "In" When OB is at high level "H" (or low level rLJ), the output signal T1n is output, and the test control signal ToE is at low level rLJ.
(or high level "H"), outputs the test-only output signal TD, n to the connection terminal Q.

Note that the connection terminal Q is a terminal to which a signal for switching between the low level rLJ state and the high level rHJ state is input when the connection terminal C is not in a high impedance state.

The output driver control circuit 50 has N O R 51 and 52
and a test control signal T. A tri-state control signal D from the connection terminal C based on E and the reset signal RST. It controls whether to output E as is or to output high level rHJ or low level rLJ regardless of the tristate control signal DoE.

The output drive circuit BO is composed of a NAND6L82, an inverter 63, an NMOS transistor 64, and an NMOS transistor B5.
One of the three states of high level "H", low level rLJ, or high impedance rZJ is output to T. That is, the output drive circuit 60 is a tri-state output circuit.

Thus, the conventional output circuit outputs the output signal Dir+ and the tri-state 1 control signal D. . is output to the output drive circuit 60 via the selection circuit 4o and the output driver control circuit 50, so regardless of the state of the internal logic circuit, the three test signal lines "Jn'" OE and RST directly
The output terminal OUT of the output drive circuit 6o is set to high level "
H'', low level rLJ or high impedance rZJ
The state of. 1ζ can be set.

[Problem to be solved by the invention] However, the conventional output circuit with the above configuration has a total of 34 M
OS } Consists of transistors. That is, four tri-state inverters 41 and 42, NAND43
4 pieces, 3 pieces of NOR51 and 52, NAND81,
132, four inverters B3 and B4, and one output transistor 65 and B6, respectively. Therefore, there was a problem that the configuration of the output circuit became complicated.

The number of elements in the output circuit was counted assuming that the tri-state inverters 41 and 42 are each realized by a clocked inverter with a small number of elements as shown in FIG.

Such a large number of elements constituting an output circuit hinders an increase in the degree of integration and is a factor in reducing yield, especially in gate arrays and the like composed of a large number of input/output circuits.

Furthermore, since the output signal D1n passes through four stages of gates before reaching the output terminal out, there is a problem that the operating speed becomes slow when the output circuit is actually operated.

The present invention has been made to solve the above problems,
It is an object of the present invention to provide an output circuit that has a small number of elements, can operate at high speed, and can be easily tested.

[Means for Solving the Problems] An output circuit according to the present invention receives a tri-state control signal and a first test control signal, inverts and outputs the tri-state control signal in the normal mode, and outputs the tri-state control signal in the test mode. When the driver control circuit outputs a high level state, the output signal from the internal logic circuit, the inverted output signal of the driver control circuit, and the second test! 1 control signal is input, and outputs an inverted output signal when in normal mode, and outputs a low level state when in test mode, an output signal, an output signal of the driver control circuit, and A second composite gate receives the third test control signal, inverts the output signal when in normal mode, and outputs a high level state when in test mode, and outputs from the composite gate and In the normal mode, one of high level, low level, and high impedance is output according to the output signal and the tristate control signal, and in the test mode, the first test control and output means for outputting any one of a high level, a low level, and a high impedance according to the states of the test signal, the second test control signal, and the third test control signal.

[Function] In the output circuit with the above configuration, in the normal mode, the driver control circuit inverts and outputs the tristate $I1 control signal, the first composite gate and the second composite gate invert and output the output signal, The output means outputs one of a high level, a low level, and a high impedance state according to the output signal and the tristate control signal.

In addition, in the case of the test mode, the driver control circuit outputs a high level state, the first composite gate outputs a low level state, the second composite gate outputs a high level state, and the output means outputs a high level state. Depending on the states of the first test control signal, the second test control signal, and the third test control signal, one state of high level, low level, and high impedance is output.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention. As shown in FIG. 1, the output circuit according to this embodiment is composed of a driver control circuit TO and an output drive circuit 20.

The driver control circuit IO is constituted by a two-way NAND, and the tristate control signal DoE is input to one input, and the test control signal Q is input to the other input.

When the test control signal Q is at a high level rI{J, the driver control circuit 10 inverts the tristate control signal DoE and outputs it to the connection terminal C. When the test control signal MQ is at a low level rLJ, the driver control circuit 10 performs tristate control. High level rHJ is output at the connection terminal regardless of signal DoE.

The driver control circuit 20 includes a composite gate 2L. 22, inverter 23, PMOS } transistor 24 and NMOS
It is composed of a transistor 25.

The composite gate 2l has a configuration in which a two-man power AND and a two-man power NOR are connected, and the output signal pln is input to one input terminal a1, and the inverter 2 is input to the other input terminal a2.
The state of the driver control circuit 10 is inputted via 3.

Furthermore, a test control signal R is input to the control terminal b1.

Further, the composite gate 22 has a configuration in which a two-manpower OR and a two-manpower NAND are connected, and the output signal DIn is input to one input terminal C, and the state of the driver control circuit 10 is input to the other input terminal C2. Ru.

Furthermore, a test control signal S is input to the control terminal d1.

4 and 5 are circuit diagrams of composite gates 21 and 22. Note that since the operations of these circuits are well known, their explanation will be omitted. As shown in FIGS. 4 and 5, the composite gate 21 operates as a NAND by inputting the test control signal R of low level rLJ, and the composite gate 22 inputs the test control signal S of high level rHJ. By doing so, it will operate as a NOR.

FIG. 6 shows the test control signal Q. ．． 3 is a circuit diagram of a test control signal generation circuit that outputs R and S. FIG. This test control signal generation circuit has two test control input signals TESTO,
Test control signals Q, R and S are generated by TESTI.

Table 1 is a truth table of the test control signal generation circuit. The operating states of the output circuit corresponding to each condition of the test control input signals TESTO and TESTI are also shown.

Table 1 By providing one test control signal generation circuit as described above, multiple output circuits can be connected and controlled simultaneously.
The number of elements in the entire integrated circuit does not increase significantly, and testing can be controlled using a simpler combination of signals.

PMOS } transistor 24 and NMOS } transistor 25 each have a gate electrode connected to the output n of composite gate 21.
1 and the output n2 of the composite gate 22 are connected, and the outputs n and n2 turn on and off, respectively.

Further, the source electrode of the PMOS transistor 24 is connected to the power supply voltage Vcc, and the source electrode of the NMOS transistor 25 is connected to the ground potential GND.

Furthermore, PMOS } transistor 24 and NMOS }
The drain electrodes of the transistors 25 are respectively connected to the output terminals out. The output terminal out outputs a signal indicating whether or not the output circuit is a good product.

Note that the output circuit shown in FIG. 1 is the driver control circuit 10.
, PMOS transistor 2 constituting the composite gate 21
6. NMOS } transistor 27 and PMOS transistor 28 and IIHOS } transistor 29 forming the composite gate 22 operate as a test control circuit.

Next, the operation of the output circuit shown in FIG. 1 will be explained with reference to the truth table in Table 2.

Table 2 First, the case where the circuit operates as a normal output circuit will be explained.

As shown in the truth table in Table 2, the test control signals Q, R
and S are respectively high level "H" and low level rLJ
At high level rHJ, the output circuit is in a normal operating state.

Therefore, the tristate control signal DoE is at high level r
At the time of HJ, the logic level of the output signal DIn of the internal logic circuit and the logic level of the output OUT are the same.

Moreover, the tri-state control signal DoE is at low level rLJ.
At this time, the output OUT becomes high impedance.

Next, the operation when testing the output circuit will be explained.

When the terminal Q becomes the low level rLJ, the terminal becomes the high level rHJ regardless of the logic level of the tristate control signal DoE, and the output circuit enters the test state.

First, both test control signals R and S are at high level rH.
When J, the output n1 of the composite gate 21 goes to low level rLJ regardless of the output signal D, and the PMOS transistor 24 turns on.

Also, the composite gate 22 operates as a 2-manual NOR with C and C2 as inputs, and since the input C is high level rHJ, the output n2 becomes low level rLJ regardless of the output signal Dr, l: NMOS transistor 25 is turned off.

Therefore, the output OUT becomes high level rHJ, and high level rHJ can be tested.

Next, test control signals R and S are both at low level rL.
When J, the composite gate 21 operates as a two-manpower NAND with human power as ah and a2, and the input a2
Since is at low level rLJ, the output nl becomes high level In rHJ regardless of the output signal D, and the PMOS transistor 24 is turned off.

Further, since the input C2 of the composite gate 22 is at the high level rHJ, the output n2 becomes the high level rHJ regardless of the output signal D, and the NMOS transistor 25 is turned on.

Therefore, the output OUT becomes the low level rLJ, and the low level rLJ can be tested.

Next, the test control signals R and S are each at a low level r
When LJ and high level rHJ are reached, the composite gate 2l operates as a two-man NAND with inputs a and a2, and the composite gate 22 operates as a two-man NOR with inputs C and C2.

Since the terminal is at the high level rHJ, the output nt of the composite gate 2l becomes the high level rHJ regardless of the logic level of the output signal D1n of the internal logic circuit. Further, the output n2 of the composite gate 22 becomes low level rLJ.

Therefore, the output OUT becomes high impedance rZJ, and high impedance rZJ can be tested.

In this way, the logic levels at the terminals of the composite gates 21 and 22 determine the l logic levels of the outputs n and n2, and the output circuit operates in the same way as a tri-state drive circuit without a test function.

As mentioned above, the output circuit is completely independent from the internal logic circuit during testing, and the test control signals Q, R, and S are used to test each state of high level rHJ, O-level rLJ, and high impedance rZJ. Can be done.

Note that the output circuit according to this embodiment is composed of 18 transistors, and the number of elements is significantly reduced compared to a conventional output circuit composed of 32 transistors.

Furthermore, since the output signal D1n reaches the output terminal 0υT only by passing through two stages of gates, higher speed operation is possible compared to the conventional output circuit which passes through four stages of gates.

By the way, in order to easily test the output circuit, N
MOS transistor 24 and PMOS transistor 25
is the tristate control signal D. It is sufficient if it can be turned on and off independently of E and the output signal Dln.

As shown in FIG. 2, a conventional output circuit connects connection terminals Q and C of an output drive circuit 60 to a tristate control signal D during testing. By forcibly setting the output signal to high level rHJ and low level rLJ regardless of the output signal Dln, the
}Ransistor 6B was being turned on and off.

Therefore, the tristate control signal DoE is connected to the connection terminal C.
In addition, the output signal D1n passes through circuits with a large number of elements, such as two or more stages of logic gates and selection circuits, before reaching the connection terminals Q.

The present invention takes advantage of the fact that if the connection terminals of the output drive circuit 60 are forcibly set to low level rLJ while testing, both the PMOS transistor 64 and the IIIMOS transistor 65 are turned off. Immediately before the connection terminal and the gate 4 of each transistor 84, 65
Test control circuits controlled by test control signals R, S, and T are provided at three locations immediately in front of the electrodes.

By providing the test control circuit, the test control circuit provided between the gate of the PMOS transistor 64 and the two-way NAND forces the gate of the PMOS transistor 64 to a low level when testing high level rHJ. All you need to do is set it to rLJ.

That is, forcibly high level rHJ and low level rLJ
Therefore, each test $1 control circuit has a simple configuration and the number of elements can be reduced.

[Effects of the Invention] As described above, according to the present invention, in the normal mode, the tri-state control signal is inverted by the driver control circuit, and the output signals by the first composite gate and the second composite gate are inverted. Accordingly, the output means outputs one of high level, low level, and high impedance according to the output signal and the tristate control signal, and in the case of the test mode, the high level state is output by the driver control circuit. The output means outputs the first test control signal, the second test control signal and the third test by the output of the first composite gate in a low level state and the second composite gate in a high level state. Since it outputs one of high level, low level, and high impedance depending on the state of the control signal, an output circuit with a small number of elements, capable of high-speed operation, and easy to test can be obtained. It has the effect of being

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional output circuit, FIG. 3 is a circuit diagram of the bus driver shown in FIG. 5 is a circuit diagram of the composite gate shown in FIG. 1, and FIG. 6 is a circuit diagram of a circuit that generates a test control signal input to the output circuit shown in FIG. 1. DESCRIPTION OF SYMBOLS 10... Driver control circuit, 20... Output drive circuit, 21, 22... Composite gate, 23... Inverter, 24... PMOS transistor, 25...
NMOS }Ran resistor. Embodiment of the present invention Figure 1 Circuit of composite gate 11 Figure 4 Circuit of composite gate 12 Figure 5 Test control signal generation circuit Figure 6 Procedural amendment (voluntary) 1998

Claims (1)

[Claims] A tri-state control signal and a first test control signal are input, and when in normal mode, the tri-state control signal is inverted and output, and when in test mode, a high level state is output. An output signal from the driver control circuit, an internal logic circuit, an inverted output signal of the driver control circuit, and a second test control signal are input, and when in normal mode, the output signal is inverted and outputted when in test mode. , a first composite gate that outputs a low level state; the output signal, the output signal of the driver control circuit, and a third test control signal are input, and when in normal mode, the output signal is inverted and output. , when in test mode,
a second composite gate that outputs a high level state, and the outputs of the first composite gate and the second composite gate are input, and when in normal mode, according to the output signal and the tristate control signal. Wow, high level.
Outputs one of low level and high impedance states, and when in test mode, depends on the states of the first test control signal, the second test control signal, and the third test control signal. An output circuit comprising: output means for outputting any one of a high level, a low level, and a high impedance state.