JP2533207B2 - Output device for semiconductor integrated circuit - Google Patents

Description

The present invention relates to an output device of a semiconductor integrated circuit, and particularly to an output device of a semiconductor integrated circuit having a display function and a large capacity memory. It is what is done.

(Prior Art) Conventionally, in a semiconductor integrated circuit having a display function and a large-capacity memory, the test of the memory portion has been performed by the method shown in the block diagram of FIG. Here, 11 is a test control signal, 12 is a CPU (central processin
g unit), 13 is an address signal from the CPU, 14 is an external terminal for address input, 15 is an address signal from an external terminal for address input, 16 is a selector, 17 is a memory, 18a to 18d are input / output devices, 19a to 19d is a general output signal, and 20a to 20d are memory input / output signals.

That is, by inputting the test control signal 11 to the selector 16, the address signal 13 from the CPU 12 is switched to the address signal 1 from the external terminal 14 for address input. As a result, the address signal 15 from the address input external terminal 14 does not pass through the CPU 12 and the address signal 21
Directly specify the address of the memory 17. After that, since the memory input / output signals 20a-20d are directly input / output from the input / output devices 18a-18d, the test time can be shortened. The number of input / output signal terminals of the memory is determined by the number of bit lines of the memory 17.

FIG. 6 is a circuit diagram showing one of the input / output devices 18a to 18d shown in the block diagram of FIG.

The input / output device 18 shares an input / output signal terminal of a memory and a general output signal terminal. And
The general output signal 19 and the memory input / output signal 20 are switched by the clock signal Test. Further, the input / output of data during the test is switched by the clock signal R /. This makes it possible to test the memory section. Here, 22 is an input / output signal terminal (pad), 23 is a positive power supply, 24 is a ground power supply, 25 is an N channel MS transistor, and 26 is a P channel MOS transistor.

On the other hand, in the case of a memory having a large memory capacity, in order to shorten the test time, a method is used in which the memory section is divided into n at the time of testing and n pieces are simultaneously tested. However, such a parallel test requires n times as many output terminals as the number of bit lines. Therefore, the number of input / output signal terminals of the memory must be increased, and data is inevitably input / output by using the display signal output terminal having a large number of terminals.

However, the display signal is a display output for lighting the liquid crystal, and its current capacity is small. Therefore, if this output terminal is used, there is a drawback that the acceleration test at the time of the test becomes difficult. Further, it may be possible to use the display signal output terminal by increasing the current capacity of the display output, but there is a disadvantage that the power consumption of the LSI increases.

(Problems to be Solved by the Invention) As described above, conventionally, in order to shorten the test time, the memory section is divided into n and a display signal output terminal is used during the test. This makes accelerated testing difficult, or
There is a drawback that the power consumption of the LSI increases.

Therefore, an object of the present invention is to provide an output device of a semiconductor integrated circuit capable of shortening a test time and performing an accelerated test without increasing a chip size and power consumption even if a memory capacity is large. To do.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, an output device of the present invention is provided with one terminal in a semiconductor integrated circuit and a plurality of output buffers connected to the one terminal. And a select gate capable of selecting one of the plurality of output buffers, and at least one of the plurality of output buffers has a larger current capacity than the other output buffers. It has been set.

(Operation) According to such a configuration, a plurality of output buffers having different current capacities are provided. Therefore, during normal operation, a general output signal is output using the output buffer with a small current capacity selected by the selection gate, and during testing, data is output with an output buffer with a large current capacity selected by the selection gate. Can be output.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the principle of an output device of a semiconductor integrated circuit according to an embodiment of the present invention.

The output device of the present invention is provided with a plurality of output buffers, for example, first and second output buffers 102 and 103 for one output signal terminal 101. In addition, first and second select gates 104 and 105 are provided as select gates capable of selecting one of the plurality of output buffers. A general output signal is input to the first selection gate 104. The output signal of the memory is input to the second selection gate 105. The test signal Test is input to the first and second selection gates 104 and 105, respectively. Then, the test signal Test is inputted, and the first selection gate 104
When the output buffer 102 is selected, a general output signal is output to the input / output signal terminal (pad) 101 via the first output buffer 102. In addition, the second selection gate 105
When the second output buffer 103 is selected by, the output signal of the memory is output to the input / output signal terminal 101 via the second output buffer 103. The current capacity of the second output buffer 103 is set to be larger than the current capacity of the first output buffer 102.

As a result, during normal operation, the first select gate 104
First output buffer having a small current capacity selected by
A general output signal is output using 102, and during the test,
Memory data can be output using the second output buffer 103 having a large current capacity selected by the second selection gate 105.

The input / output of the memory data during the test is switched by the clock signal R / (not shown) as in the conventional case.

FIG. 2 is a schematic circuit diagram of an output device of a semiconductor integrated circuit according to an embodiment of the present invention.

The display signal line 2 and the test signal line 3 are connected to the input terminal of the NOR gate 1. The test signal line 3 is connected to the input terminal of the NAND gate 4 via the display signal line 2 and the inverter I ₁ . The output terminal of the NOR gate 1 is connected to the gate of the N-channel MOS transistor TrN1. The output terminal of the NAND gate 4 is a P channel MOS
It is connected to the gate of the transistor TrP1 and the gate of the N-channel MOS transistor TrN2 via the inverter I ₂ . The source of the transistor TrN1 is the ground power supply.
It is connected to V _SS and its drain is connected to pad 5. The sources of the transistors TrP1 and TrN2 are connected to the positive power supply V _DD, and the drains thereof are the pad 5
It is connected to the. Note that the transistor TrP1 and the transistor TrN2 form a transmission gate.

Further, the test signal line 3 is connected to the input terminal of the NOR gate 6 via the data line 7 and the inverter I ₃ . The test signal line 3 is connected to the input terminal of the NAND gate 8 via the data line 7 and the inverters I ₃ and I ₄ . The output terminal of the NOR gate 6 is connected to the gate of the low-level output N-channel MOS transistor TrN3. The output terminal of the NAND gate 8 is connected to the gate of the high-level output P-channel MOS transistor TrP2.
The source of the transistor TrN3 is connected to the ground power supply V _SS, and the drain thereof is connected to the pad 5. The source of the transistor TrP2 is connected to the positive power supply V _DD, and the drain thereof is connected to the pad 5.

The NOR gate 1, the NAND gate 4 and the like constitute the first selection gate 104, and the NOR gate 6, the NAND gate 8 and the like constitute the second selection gate 105. The first output buffer 10 including the transistors TrN1, TrN2, TrP1 etc.
2 are configured. The transistors TrN3, TrP2, etc. form a second output buffer 103. Also, the second
The current capacity of the output buffer 103 of the first output buffer 102
Transistor TrN3 and
The current supply capacity of TrP2 depends on the transistors TrN1, TrN2 and TrN.
It is larger than the current supply capacity of P1.

Next, the operation of the output device of the semiconductor integrated circuit will be described in detail with reference to FIG. Here, in order to make the following explanation understandable accurately and easily, FIG.
The truth chart of NOR gate, its symbol is shown in Fig. 4 (b), its time chart is shown in Fig. 4 (c), and Fig. 4 (a).
The truth diagram of the NAND gate, its symbol in (b).
The time chart is shown in FIG.

During normal operation, the test signal Test on the test signal line 3 is at a low level (hereinafter abbreviated as “L”). Therefore, a high level (hereinafter abbreviated as “H”) is input to the NOR gate 1 from the test signal line 3 and to the NAND gate 4 from the test signal line 3 via the inverter I ₁ . To do. Therefore, according to the segment signal (“L” or “H”) of the display signal line 2, the transistor TrN1, the transistors TrP1 and TrN2 are turned on or off, respectively, and the display signal is output from the pad 5. On the other hand, the NOR gate 6 via the inverter I ₃ from the test signal line 3, "H", the NAND gate 8 from the test signal line 3 via the inverter I ₃ and I ₄ "L" is inputted. That is, the output of the NOR gate 6 is always "L" and the output of the NAND gate 8 is "H" regardless of the memory output signal ("L" or "H") of the data line 7. Therefore, the transistors TrP2 and TrN3 both remain off.

Further, at the time of testing, the test signal Test of the test signal line 3 becomes “H”. Therefore, the NOR gate 1 is connected to the test signal line 3 from "H", and the NAND gate 4 is connected to the test signal line 3
“L” is input from each inverter via the inverter I ₁ . That is, regardless of the segment signal (“L” or “H”) of the display signal line 2, the output of the NOR gate 1 is always “L” and the output of the NAND gate 4 is
Output becomes "H". Therefore, the transistor TrN1 and the transistors TrP1 and TrN2 remain in the off state. On the other hand, the NOR gate 6 is connected to the inverter I ₃ via the test signal line _3.
Through the "L", the NAND gate 8 from the test signal line 2 via the inverter I ₃ and I ₄ "H" is inputted. Therefore, the output signal (“L” or “H”) of the memory on the data line 7
Accordingly, the transistors TrP2 and TrN3 are turned on or off, respectively, and the memory data can be read from the pad 5.

According to such a configuration, the first and second output buffers 102 and 103 having different current capacities are provided. For this reason,
During normal operation, a segment signal is output using the first output buffer 102 having a small current capacity selected by the first selection gate 104, and at the time of testing, the current capacity selected by the second selection gate 105 is large. Memory data can be output using the second output buffer 103. That is, the power consumption is suppressed during the normal operation, the accelerated test can be performed during the test, and an inexpensive LSI can be provided.

In the above-described embodiment, the transistors TrP2 and TrN3 for outputting memory data can be dummy transistors provided for protection. in this case,
The output device can be configured without increasing the chip area. Also, the first and second output buffers 10
Although 2,103 are connected between the positive power supply V _DD and the ground power supply V _SS , they may be connected between the ground power supply and the negative power supply. Further, the first and second output buffers 102 and 103 are connected to the positive power supply V _DD.
Although it is composed of P-channel and N-channel type MOS transistors connected in series between the power supply and the ground power supply V _SS , it may be composed of a single MOS transistor.

[Effects of the Invention] As described above, according to the output device of the semiconductor integrated circuit of the present invention, the following effects are obtained.

Equipped with multiple output buffers with different current capacity, during normal operation, the output buffer with a small current capacity selected by the select gate is used to output segment signals, and during test, the large current capacity selected by the select gate is used. Memory data is output using the output buffer. Therefore, even if the memory capacity is large, it is possible to provide the output device of the semiconductor integrated circuit capable of shortening the test time and performing the accelerated test without increasing the chip size and the power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of an output device for a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram specifically showing an output device for a semiconductor integrated circuit according to an embodiment of the present invention. , Fig. 3 (a) Diagram showing truth chart of NOR gate,
FIG. 3 (b) is a diagram showing a symbol of a NOR gate, FIG. 3 (c) is a diagram showing a time chart of FIG. 3 (b), and FIG. 4 (a) is a diagram showing a truth diagram of a NAND gate. Fig. 4 (b)
Is a diagram showing a symbol of a NAND gate, FIG. 4 (c) is a diagram showing a time chart of FIG. 4 (b), FIG. 5 is a block diagram for explaining a conventional memory section test, and FIG.
The drawing is a circuit diagram showing one of the input / output devices shown in the block diagram of FIG. 1,6 …… NOR gate, 2 …… display signal line, 3 …… test signal line, 4,8 …… NAND gate, 5 …… pad, 7 …… data line, 101 …… input / output signal terminal, 102 ...... First output buffer, 103 ...... Second output buffer, 104 ...... First selection gate, 105 ...... Second selection gate, TrN1 to TrN3 ...... N
Channel MOS transistors, TrP1 and TrP2 ... P-channel MOS transistors, I _{1 to} I ₄ ...... Inverter, V _DD …… Positive power supply, V _SS …… Negative power supply.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 62-8195 (JP, A) JP 63-7600 (JP, A)

Claims (1)

(57) [Claims] 1. An output device of a semiconductor integrated circuit having a display function and a large capacity memory, a display signal output terminal, a first output buffer having a small current capacity connected to the display signal output terminal, A second output buffer connected to the display signal output terminal and having a current capacity larger than the current capacity of the first output buffer, a test signal, and a display signal for lighting the liquid crystal are input,
A first select gate that outputs the display signal from the first output buffer and deactivates the second output buffer when the test signal is at a first level; the test signal and the large capacity A second select gate for outputting the memory data from the second output buffer and deactivating the first output buffer when the memory data of the memory is input and the test signal is at the second level; An output device for a semiconductor integrated circuit, comprising: