KR100480566B1 - Signal generator for testing redundancy memory cell of semiconductor memory device - Google Patents

Abstract

The present invention discloses a redundancy memory cell test signal generator of a semiconductor memory device. It is used to test an external redundancy signal input into a semiconductor memory device through a pad and a row address buffer output signal output from a row address buffer inside the semiconductor memory device to test either a low redundancy memory cell or a column redundancy memory cell. As an input and its output signal is input to a low redundancy memory cell and a column redundancy memory cell, and when the row address buffer output signal is enabled before the external redundancy signal, any of a low redundancy memory cell test operation and a column redundancy memory cell test operation Execute one of the low redundancy memory cell test operation and the column redundancy memory cell test operation if the external redundancy signal is enabled before the row address buffer output signal. Let's do it.

Description

Signal generator for testing redundancy memory cell of semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a redundancy memory cell test signal generator of a semiconductor memory device.

As semiconductor memory devices become more integrated, the importance of redundant memory cells, that is, redundancy memory cells, is becoming more important than normal memory cells. When a defect occurs in a predetermined memory cell among the normal memory cells, the redundancy memory cell becomes a redundant memory cell. This is because the yield can be maximized by replacing.

The redundancy memory cell is divided into a row redundancy memory cell and a column redundancy memory cell. If the row address of the normal memory cell is bad, the redundancy memory cell is replaced with the row redundancy memory cell. Replaced by a cell

1 is a block diagram illustrating a redundancy memory cell test signal generator of a conventional semiconductor memory device.

Referring to FIG. 1, a redundancy memory cell is divided into a low redundancy memory cell 14 and a column redundancy memory cell 15, and the low redundancy signal RR is external to the first pad 16 outside the semiconductor memory device 11. When the low redundancy memory cell test signal generator 12 is input to the low redundancy memory cell test signal generator 12, the low redundancy memory cell test signal generator 12 generates a low redundancy memory cell test signal R, thereby testing the low redundancy memory cell 14. The action is executed.

In addition, when the column redundancy signal CR is input to the column redundancy memory cell test signal generator 13 of the semiconductor memory device 11 through the second pad 17, the column redundancy memory column test signal generator 13 may perform column redundancy. By generating the memory cell test signal C, the column redundancy memory cell 15 test operation is executed.

2 and 3 show circuit diagrams of the low redundancy memory cell test signal generator 12 and the column redundancy memory cell test signal generator 13 shown in FIG. 1, respectively.

2 and 3, the low redundancy memory cell test signal generator 12 has a structure in which first and second inverters 21 and 22 are connected in series, and the column redundancy memory cell test signal generator ( 13 is a structure in which the third and fourth inverters 31 and 32 are connected in series. In front of the first and third inverters 21 and 31, noise removing means including NMOS transistors 23 · 24 or 33 · 34 is provided.

The low redundancy memory cell test signal R and the column redundancy memory cell test signal C may be less than the low redundancy signal RR and the column redundancy signal CR due to the inverters 21. 22 or 31. There is a delay.

4 and 5 are timing diagrams of signals used in the circuit diagrams of FIGS. 2 and 3.

Referring to FIG. 4, when the low redundancy signal RR and the column redundancy signal CR are logic low L, the low redundancy test signal R and the column redundancy test signal C are transferred to the logic low L. It is disabled so that the test operation is not performed on the low redundancy memory cell test operation and the column redundancy memory cell. At this time, the semiconductor memory device performs a read / write or normal memory cell test operation of data.

Referring to FIG. 5, when the low redundancy signal RR is enabled from a logic low L to a logic high H, the low redundancy test signal R is delayed for a predetermined time and then logic high at the logic low L. (H), the semiconductor memory device executes a low redundancy memory cell test operation without executing a read / write or normal memory cell test operation of data. In addition, when the column redundancy signal CR is enabled from the logic low L to the logic high H, the column redundancy test signal R becomes a logic high H from the logic low L after a predetermined time delay. The semiconductor memory device performs a column redundancy memory cell test operation without performing a read / write of data or a normal memory cell test operation.

That is, the low redundancy signal RR input through the first pad (16 in FIG. 1) must be enabled to test the low redundancy memory cell, and the second pad (17 in FIG. 1) to test the column redundancy memory cell. It is necessary to enable the column redundancy signal (CR) input through

Therefore, the redundancy memory cell test signal generator of the semiconductor memory device as described above receives a signal for testing a low redundancy memory cell and a column redundancy memory cell through two pads, and the pad occupies a large area in the layout of the semiconductor device. As a result, there is an obstacle in minimizing chip size.

An object of the present invention is to provide a redundancy memory cell test signal generator for a semiconductor memory device which executes any one of a redundancy memory cell test operation and a column redundancy memory cell test operation by inputting one external redundancy signal. have.

In order to achieve the above object, the present invention provides an external redundancy signal input for testing one of a low redundancy memory cell and a column redundancy memory cell through one pad, and a row address buffer output from a row address buffer inside the semiconductor memory device. A latch circuit for receiving an output signal as an input; An inverter connected to an output terminal of the latch circuit; A first switching device configured to transmit an output signal of the inverter to any one of the low redundancy memory cell and the column redundancy memory cell; And a second switching element configured to transfer an output signal of the latch circuit to another one of the low redundancy memory cell and the column redundancy memory cell.

The redundancy memory cell test signal generator executes any one of a low redundancy memory cell test operation and a column redundancy memory cell test operation when the external redundancy signal is enabled before the row address buffer output signal, and the row address buffer output signal is executed. If is enabled before the external redundancy signal, another one of the low redundancy memory cell test operation and the column redundancy memory cell test operation is executed.

An NMOS transistor is provided at an output terminal of the first switching element and the second switching element, and the switching on / off of the first switching element and the second switching element and the turn on / off of the NMOS transistor are performed by the external redundancy signal. It is preferred that the off is controlled.

Therefore, the redundancy memory cell test signal generator of the semiconductor memory device according to the present invention uses a low redundancy memory cell test operation and a column redundancy memory by using a timing difference in which an external redundancy signal and an internal row address buffer output signal are enabled / disabled. Execute one of the cell test operations.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram illustrating a redundancy memory cell test signal generator of a semiconductor memory device according to the present invention.

Referring to FIG. 6, a redundancy memory cell is divided into a row redundancy memory cell 64 and a column redundancy memory cell 65.

The redundancy memory cell test signal generator 62 receives the external redundancy signal RC input from the outside of the semiconductor device 61 through the pad 66 and the row address buffer output signal A output from the row address buffer 63. The low redundancy memory cell test signal R and the column redundancy memory cell test signal C are outputted as inputs.

The low redundancy memory cell test signal R is input to the low redundancy memory cell 64 to execute a low redundancy memory cell 64 test operation, and the column redundancy memory cell test signal C is the column redundancy memory cell. Input to 65 to execute the column redundancy memory cell 65 test operation.

) 신호를 패드(67)를 통해 입력하여 CMOS 레벨의 로우 어드레스 버퍼 출력 신호(A)로 변환시키는 역할을 한다.The row address buffer 63 has a row address strobe bar (TTL) level (transistor transistor logic) level.

) Is input through the pad 67 to convert the row address buffer output signal A at the CMOS level.

FIG. 7 is a circuit diagram of the redundancy memory cell test signal generator 62 of FIG. 6 shown in FIG.

The structure of the redundancy memory cell test signal generator 62 of FIG. 6 includes a latch circuit 83 which receives an external redundancy signal RC and a row address buffer output signal A, and an output terminal of the latch circuit 83. A first inverter 73 connected to (n1), a first switching element 81 and the latch circuit 83 which transmits the output signal of the first inverter 73 to the column redundancy memory cell (65 in FIG. 6). ) Is a second switching element 82 that transmits the output signal to the low redundancy memory cell (64 in FIG. 6).

The latch circuit 83 includes a first logic gate 79 and a second logic gate 80, wherein the first logic gate 79 includes an output signal of the second logic gate 80 and the external redundancy. The signal RC is input, and the second logic gate 80 receives the output signal of the first logic gate 79 and the row address buffer output signal A.

The first inverter 73 includes a low redundancy memory cell test signal R and a column redundancy memory cell test signal C when the first switching element 81 and the second switching element 82 are switched on. Only one of them is enabled.

NMOS transistors 77 and 78 are connected to output terminals n2 and n3 of the first switching element 81 and the second switching element 82, respectively. It is turned on or turned off according to the output signal of the second inverter 76 which inverts the external redundancy signal RC.

That is, a low redundancy memory cell test signal for testing a low redundancy memory cell (64 in FIG. 6) by adjusting a timing at which the external redundancy signal RC and the low address buffer output signal A are enabled or disabled. (R) or a column redundancy memory cell test signal C for testing the column redundancy memory cell (65 in FIG. 6) is generated.

The first logic gate 79 and the second logic gate 80 may be configured as a NAND gate or a NOR gate, and the first logic gate 79 and the second logic gate 80 as a NAND gate. The case where the first switching element 81 and the second switching element 82 are made of a transfer gate will be described as an example.

If any one of an external redundancy signal RC and an output signal of the second NAND gate 72 is a logic low, the output of the first NAND gate 71 becomes a logic high, and the external redundancy signal RC and the first If the output signals of the two NAND gates 72 are both logic high, the output becomes logic low. When the second NAND gate 72 is any one of the row address buffer output signal A and the output signal of the first NAND gate 71, the output becomes logic high and the row address buffer output signal ( If both A) and the output signal of the first NAND gate 71 are logic high, the output becomes logic low.

Switching ON / OFF of the first transmission gate 74 and the second transmission gate 75 is controlled by the external redundancy signal RC, that is, the external redundancy signal RC is logic. When disabled, the first transfer gate 74 and the second transfer gate 75 are switched off, and the NMOS transistors 77 and 78 are turned on so that the first transfer gate 74 is turned on. And the output terminals n2 and n3 of the second transmission gate 75 are grounded. Therefore, the low redundancy memory cell test signal R and the column redundancy memory cell test signal C do not occur. When the external redundancy signal RC is enabled from logic low to logic high, the first transfer gate 74 and the second transfer gate 75 are switched on to output the output signal of the second NAND gate 72. In this case, since the logic levels of the low redundancy memory cell test signal R and the column redundancy memory cell test signal C are opposite due to the first inverter 73, the low redundancy memory cell (64 in FIG. 6) is tested. Any one of an operation and a column redundancy memory cell (65 in FIG. 6) test operation is executed.

8 to 10 are timing diagrams of signals used in the circuit diagram of FIG.

Referring to FIG. 8, when the external redundancy signal RC is disabled to logic low, the first transfer gate (74 of FIG. 7) and the second transfer gate (75 of FIG. 7) are switched off and the NMOS transistor (77 and 78 in Fig. 7) is turned on. As a result, the output terminals (n2 and n3 of FIG. 7) of the first transfer gate (74 of FIG. 7) and the second transfer gate (75 of FIG. 7) are grounded to form a low redundancy memory cell test signal R. The column redundancy memory cell test signal C is not generated.

As described above, in the state in which the external redundancy signal RC is disabled in a logic low state, even when the row address buffer output signal A is disabled in a logic low state or enabled in a logic high state, a low redundancy memory cell test signal R is performed. And the column redundancy memory cell test signal C is kept at a logic low level, so that the semiconductor memory device performs a normal memory cell test operation or a read / write operation of data without executing a low redundancy memory cell test operation and a column redundancy memory cell test operation. Run

Referring to FIG. 9, when the external redundancy signal RC is enabled from logic low to logic high while the row address buffer output signal A is disabled to logic low, the first transfer gate (FIG. 74 of 7 and the second transfer gate 75 of FIG. 7 are switched on and NMOS transistors 77 and 78 of FIG. 7 are turned off. The output terminal (n1 of FIG. 7) of the second NAND gate (72 of FIG. 7) is logic high and the output signal of the second NAND gate (72 of FIG. 7) is the first inverter (73 of FIG. 7). Inverted while passing, the column redundancy memory cell test signal C is kept at a logic low, and the low redundancy memory cell test signal R is at a logic high like the output terminal n1 of the second NAND gate 72. .

Subsequently, when the row address buffer output signal A is enabled from logic low to logic high, the output terminal (n1 in FIG. 7) of the second NAND gate (72 in FIG. 7) remains logic high, thereby providing the low redundancy memory cell. The test signal R and the column redundancy memory cell test signal C are not changed.

In other words, when the external redundancy signal RC is enabled to logic high before the low address buffer output signal A, only the low redundancy memory cell test signal R is logic high so that the semiconductor memory device performs a low redundancy memory cell test operation. Run

Referring to FIG. 10, when the row address buffer output signal A is logic high enabled and the external redundancy signal RC is disabled to logic low, the first transfer gate (74 of FIG. 7) may be used. And the second transfer gate 75 of FIG. 7 is switched off and the NMOS transistors 77 and 78 of FIG. 7 are turned on so that the low redundancy memory cell test signal R and the column redundancy memory cell test signal C Remains logic low.

In the above state, when the external redundancy signal RC is enabled with logic high, the output terminal (n1 of FIG. 7) of the second NAND gate 72 of FIG. 7 becomes logic low and the first transfer gate ( 74 in FIG. 7 and the second transfer gate 75 in FIG. 7 are switched on. As a result, the low redundancy memory cell test signal R remains at a logic low state, but the column redundancy memory cell test signal C is at a logic high.

That is, when the row address buffer output signal A is enabled to logic high before the external redundancy signal RC, only the column redundancy memory cell test signal R is logic high, so that the semiconductor memory device performs a column redundancy memory cell test operation. Run

Accordingly, the present invention executes a low redundancy memory cell test operation or a column redundancy memory cell test operation according to the timing at which the row address buffer output signal A and the external redundancy signal RC are enabled / disabled.

The present invention is not limited to this, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, the redundancy memory cell test signal generator of the semiconductor memory device according to the present invention uses low redundancy by using a timing difference in which an external redundancy signal and an internal low address buffer output signal are enabled / disabled. Since any one of the memory cell test operation and the column redundancy memory cell test operation can be executed, and only one pad to which the external redundancy signal is input is required, the chip size can be minimized when the semiconductor memory device is laid out.

1 is a block diagram illustrating a redundancy memory cell test signal generator of a conventional semiconductor memory device.

2 and 3 show circuit diagrams of the low redundancy memory cell test signal generator and the column redundancy memory cell test signal generator shown in FIG. 1, respectively.

4 and 5 are timing diagrams of signals used in the circuit diagrams of FIGS. 2 and 3.

6 is a block diagram illustrating a redundancy memory cell test signal generator of a semiconductor memory device according to the present invention.

FIG. 7 is a circuit diagram of the redundancy memory cell test signal generator shown in FIG.

8 to 10 are timing diagrams of signals used in the circuit diagram of FIG.

Claims (14)

A latch circuit for inputting an external redundancy signal input to test one of a low redundancy memory cell and a column redundancy memory cell through one pad and a row address buffer output signal output from a row address buffer inside the semiconductor memory device; An inverter connected to an output terminal of the latch circuit; A first switching device configured to transmit an output signal of the inverter to any one of the low redundancy memory cell and the column redundancy memory cell; And And a second switching element configured to transfer an output signal of the latch circuit to another one of the low redundancy memory cell and the column redundancy memory cell. 2. The redundancy memory cell test signal generator of claim 1, wherein the latch circuit comprises a first logic gate and a second logic gate. 3. The logic circuit of claim 2, wherein the first logic gate receives an output signal of the second logic gate and the external redundancy signal, and the second logic gate outputs an output signal of the first logic gate and the row address buffer output. A redundancy memory cell test signal generator of a semiconductor memory device, characterized in that the signal is input. The method of claim 2, wherein the first logic gate and the second logic gate is A redundancy memory cell test signal generator of a semiconductor memory device, wherein the output signal is a NAND gate whose logic signal is low only when the input signals are all logic high. The method of claim 2, wherein the first logic gate and the second logic gate is The redundancy memory cell test signal generator of a semiconductor memory device, wherein the output signal is a noah gate whose logic signal is high only when the input signals are all logic low. The method of claim 1, wherein the first switching element and the second switching element A redundancy memory cell test signal generator for a semiconductor memory device, comprising a transfer gate. The redundancy memory cell test signal generator of claim 1, wherein the on / off of the first switching element and the second switching element is controlled by the external redundancy signal. The method of claim 1, wherein when the external redundancy signal is enabled before the row address buffer output signal, one of a low redundancy memory cell test operation and a column redundancy memory cell test operation is executed. And executing the other of the low redundancy memory cell test operation and the column redundancy memory cell test operation when the external redundancy signal is enabled before the external redundancy signal. 2. The redundancy memory cell test signal generator of claim 1, wherein if the external redundancy signal is disabled, neither the redundancy memory cell test operation nor the column redundancy memory cell test operation is executed. 2. The redundancy of the semiconductor memory device of claim 1, wherein the latch circuit is configured of NAND gates and the external redundancy signal is enabled before the row address buffer output signal to perform a test operation on a low redundancy memory cell. Memory cell test signal generator. The semiconductor memory device of claim 1, wherein the latch circuit comprises the NAND gates and executes the low redundancy memory cell test operation when the row address buffer output signal is enabled before the external redundancy signal. Redundant memory cell test signal generator. According to claim 1, wherein the output terminal of the first switching element and the second switching element And a NMOS transistor controlled by the external redundancy signal. 13. The redundancy memory cell test signal generator of claim 12, wherein the NMOS transistors are turned off when the external redundancy signal is enabled. The redundancy memory cell test signal generator of claim 12, wherein when the external redundancy signal is disabled, the NMOS transistors are turned on to ground the output terminals of the first switching element and the second switching element. .

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