KR100304280B1 - Pipeline circuit of semiconductor device - Google Patents

Abstract

PURPOSE: A pipeline circuit of semiconductor device is provided to prevent malfunction of a pipe register owing to coupling noise of a data line at a high-speed operation. CONSTITUTION: An input switch device(110) receives a high-data pulse signal(D-H) and a low-data pulse signal(D-L) to output predetermined data to the first node(N1) and the second node(N2), respectively. A latch device(120) receives and latches data signals on the first and second nodes(N1,N2), and outputs the latched data signals to the third and fourth nodes(N3,N4) respectively. An output switch device(130) operates in response to an output enable zero signal(OeO), and transfers the data signals on the third and fourth nodes(N3,N4) to a data output stage.

Description

Pipeline device of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline apparatus that delivers data signals sequentially generated by an externally input synchronized signal. In particular, the present invention relates to coupling noise generated by narrowing and lengthening data lines as semiconductor devices become highly integrated. It relates to a pipe register for preventing the malfunction of the data signal.

Until now, a switching device connected in series with a signal transmission path in an internal device has been used to open and close the switching device in accordance with a clock signal input from the outside.

1 shows an example of a conventional pipe register, and a plurality of pipe registers are connected in parallel to a data bus line to store and transmit data signals sequentially generated by an external synchronization signal.

First, in the normal operation, the reset zero signal Rst0 becomes "high" so that the first node N1 and the second node N2 have a potential of "low" level and are in a standby state.

When the "high" data is input in the standby state, the high data pulse signal DH becomes "low" and the low data pulse signal DL becomes "high" so that the first PMOS transistor MP1 is turned on. The on and third PMOS transistors MP3 are turned off.

Subsequently, when the input enable zero signal En0 is input, the second PMOS transistor MP2 and the fourth PMOS transistor MP4 are turned on so that the potential of the first node N1 is “high”. Will rise.

On the other hand, the second node N2 maintains the "low" potential of the standby state.

Subsequently, each potential on the first node N1 and the second node N2 is stored by the latching device for a predetermined time.

Finally, when the output enable zero signal Oe0 is input, the fifth and sixth PMOS transistors MP6 and the third and fourth NMOS transistors MN4 are turned on so that the third and fourth nodes are turned on. The signal is sent to the data output.

So far, the "high" data has been input to the pipe register. When the "low" data is input, the low data pulse signal DL becomes "low" and the high data pulse signal DH becomes "high." The first PMOS transistor MP1 and the third PMOS transistor MP3 are input to the gate terminal to perform the same operation.

Therefore, the operation description thereof will be omitted.

As the semiconductor devices become highly integrated and the data lines become narrower and longer, coupling noise is generated in the data lines during high speed operation.

For example, when "high" data is input, in the normal operation, the first node N1 has a "high" potential and the second node N2 has a "low" level potential due to coupling noise of the data line. The third PMOS transistor MP3 of the input switch device is affected.

That is, the potential of the "high" level input to the gate terminal of the third PMOS transistor MP3 drops due to the coupling noise to turn on the third PMOS transistor MP3. have.

In this case, the potential on the second node N2 does not have a potential in a standby state, but has the same potential level as that of the first node N1, which may cause an unexpected malfunction.

In other words, a normal data signal is input to one data line and a noise signal is input to another data line.

In this case, the potentials on the third node N3 and the fourth node N4 have the same level, and thus an unwanted output signal is generated.

As described above, in the pipe register having the conventional configuration, there is a problem that data loss or malfunction may occur due to the inability to effectively control the input noise.

Accordingly, the present invention has been devised to solve this problem, and is intended to prevent malfunction of pipe registers caused by coupling noise of data lines during high speed operation.

1 is a circuit diagram showing a pipe resistor according to the prior art;

2 is a circuit diagram showing a pipe register according to a first embodiment of the present invention;

3 is a circuit diagram showing a pipe register according to a second embodiment of the present invention;

4 is a circuit diagram showing a pipe register according to a third embodiment of the present invention;

* Explanation of symbols for main parts of the drawings

10, 20, 30, 100, 200, 300, 1000, 2000: Pipe register

11, 110, 1300, 2300: Input switch device

12, 120, 1300, 2300: Latch device

13, 130, 1400, 2400: Output switch device

1200, 2200: Coupling Noise Control

According to a preferred embodiment of the present invention for achieving the above object, the pipeline apparatus for transmitting the data signal sequentially generated by the external synchronization signal, the potential of the same level by operating by a predetermined data pulse signal in the standby state Switching means for generating a first node and a second node, and generating an opposite level potential to the first node and the second node by operating a predetermined data pulse signal in an active state, and the first and second nodes. Latching means connected between a node and third and fourth nodes to latch the data on the first or second node for a predetermined time and then control an abnormal potential on the first or second node to prevent the occurrence of the same data; And output switching means connected between the third and fourth nodes and a data output terminal to output data on the third and fourth nodes. The features.

According to still another preferred embodiment of the present invention, a pipeline apparatus for transmitting data signals sequentially generated by an external synchronization signal operates by a predetermined data pulse signal in a standby state to generate potentials of the same level in a first node. And an input switching means for generating at the second node and operating with a predetermined data pulse signal in an active state to generate opposite level potentials at the first node and the second node, and coupled to an output terminal of the input switching means. Coupling noise control means for controlling abnormal data on the first or second node according to noise, and connected between the first and second nodes and third and fourth nodes, and data on the first or second node. Latching means for latching a predetermined time, and connected between the third and fourth nodes and the data output terminal, It is characterized by including the output switching means for outputting the output.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, the first, second and third embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 shows a first embodiment of the present invention, which is composed of a plurality of pipe registers connected in parallel to data lines.

Here, each pipe register has the same configuration as described below, and latches the data signal generated by the external synchronization signal in "sequential order" and delivers the data to the data output terminal.

First, referring to the configuration of the pipe register, an input switch for receiving a high data pulse signal DH and a low data pulse signal DL and outputting a predetermined data signal to the first node N1 and the second node N2. The device 110 receives the data signals on the first node N1 and the second node N2 and outputs data signals to the third node N3 and the fourth node N4 after latching for a predetermined time. A latch device 120 and an output switch device 130 which is operated by an output enable zero signal Oe0 to transfer data signals on the third and fourth nodes N4 to a data output terminal.

The input switch device 110 is connected in series between a power supply voltage terminal Vcc and the first node N1, and includes a first input signal for inputting a high data pulse signal DH and an input enable zero signal En0 to a gate, respectively. And a first NMOS transistor (MP1, MP2) and a first zero transistor (Rst0) applied to a gate and connected between the first node (N1) and a ground voltage terminal (Vss). Third and third connected in series between MN1, a power supply voltage terminal Vcc, and the second node N2 and to which a low data pulse signal DL and the input enable zero signal En0 are respectively applied to a gate; The second NMOS transistor MN2 is connected to the second node N2 and the ground voltage terminal Vss by applying the reset zero signal Rst0 to a fourth PMOS transistor MP3 and MP4 and a gate. It consists of.

The latch device 120 includes a first NAND gate having one input terminal connected to the first node N1, the other input terminal connected to the fourth node N4, and an output terminal connected to the third node N3. And a first inverter IV1 for inverting the signal on the third node N3 and outputting the inverted signal to the first node N1, and one input terminal of which is connected to the second node N2, and the other input terminal of which is connected to the second node N2. A second NAND gate connected to the third node N3 and having an output terminal connected to the fourth node N4, and inverting a potential on the fourth node N4 to output to the second node N2; It consists of the 2nd inverter IV2.

The output switching device 130 is provided with an output enable zero signal Oe0 and an inverted signal of the output enable zero signal Oe0 as a gate, respectively, and are connected in parallel between the third node N3 and the data output terminal. The third NMOS transistor MN3 and the fifth PMOS transistor MP5 and a gate inverted signal of the output enable zero signal Oe0 and the output enable zero signal Oe0 are respectively applied to the gate. The fourth NMOS transistor MN4 and the sixth PMOS transistor MP6 connected in parallel between the fourth node N4 and the data output terminal, and the output enable zero signal Oe0 to be inverted. And a third inverter IV3 output to the gate terminal of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6.

First, when the reset zero signal Rst0 is applied, the first and second NMOS transistors MN2 are turned on so that the first and second nodes N2 have potentials of the "low" level.

Second, when the "high" data is input in the normal operation, the high data pulse signal DH becomes "low" and the low data pulse signal DL becomes "high" so that the first PMOS transistor MP1 is turned on. Turn-on, the third PMOS transistor MP1 is turned off.

Subsequently, when the input enable zero signal En0 is applied, the second PMOS transistor MP2 is turned on and the fourth PMOS transistor MP4 is turned off.

Accordingly, the "high" potential is generated at the first node N1, and the "low" potential of the standby state is maintained on the second node N2.

A "high" potential on the first node N1 and a "high" potential on the fourth node N4 in the standby state are inputted to the first NAND gate output terminal, and a "low" potential is outputted to the second NAND gate output terminal. The "low" potential on the two nodes N2 and the "low" potential on the third node N3 are input to output the "high" potential.

The "low" potential on the third node N3 is inverted by the first inverter IV1, and a "high" potential is output again to the first node N1, and the "high" potential on the fourth node N4. The potential is inverted by the second inverter IV2 to again output the "low" potential on the second node N2.

That is, when high data is input, the latch device latches the high data.

Subsequently, when the output enable zero signal Oe0 is applied, the output switch device is turned on so that the corresponding potential on the third node N3 and the fourth node N4 is transferred to the data output terminal, thereby completing the operation of the pipe register. do.

By the way, the description so far has described the operation of one register. The operation of a plurality of pipe registers is performed as described above sequentially. For example, when the first pipe register is operated, each pipe below the second pipe register is operated. The register is in standby state.

Third, when coupling noise is generated in the data line and affects the PMOS transistor of the input switch device, the second node N2 in normal operation has a "high" level.

At this time, the first node N1 is " high " and the second node N2 is " high. &Quot;

In the present invention, since the first node N1 is "high" and the fourth node N4 is the first "high", the third node N3 is "low".

The "low" of the third node N3 is input to one terminal of the second NAND gate. Accordingly, even when the second node N2 becomes "high", the fourth node N4 maintains the "high" level as in the normal state by the "low" potential on the third node N3.

According to the present invention, even when the potential on the second node N2 changes due to the coupling noise of the data line, the potential on the fourth node N4 has a function of filtering noise by keeping the potential of the steady state as it is.

Subsequently, when the output enable zero signal Oe0 is input, the corresponding signal on the third and fourth nodes N4 is transmitted to the data output terminal through the output switch device.

In the above, the case where the high data is input has been described as an example. When the low data is input, the low data pulse signal DL is " low " and the high data pulse signal DH is " High "and the first node N1 has a" low "and the second node N2 has a" high "potential.

Therefore, when coupling noise occurs, the potential on the first node N1 changes to "high", but the third node N3 maintains "high" as described above.

FIG. 3 shows a second embodiment of the present invention, and FIG. 4 shows a third embodiment of the present invention, which controls the potentials on the first node N1 and the second node N2 as compared with the first embodiment. The overall signal flow is the same with the difference in the control configuration.

First, the second embodiment will be described.

Multiple pipe registers are connected in parallel to a data line, and represent one pipe register.

According to the configuration, the input switch device 1100 that receives the high data pulse signal DH and the low data pulse signal DL and outputs a predetermined data signal to the first node N1 and the second node N2. And a coupling noise control device 1200 for controlling the potentials on the first and second nodes N2 and a data signal on the first and second nodes N1 and N2 for a predetermined time. Later, the latch device 1300 outputs a data signal to the third node N3 and the fourth node N4 and the output enable zero signal Oe0, respectively, to operate the third and fourth nodes N4. It is composed of an output switch device 1400 for transmitting a data signal on the data output stage.

The input switch device 1100 is connected in series between a power supply voltage terminal Vcc and the first node N1, and includes a first input signal for inputting a high data pulse signal DH and an input enable zero signal En0 to a gate, respectively. The first NMOS transistor MN1 is connected to the first node N1 and the ground voltage terminal Vss by applying a second PMOS transistor MP2 and a reset zero signal Rst0 to the gate. And third and fourth blood terminals connected in series between a power supply voltage terminal Vcc and the second node N2 and to which a low data pulse signal DL and the input enable zero signal En0 are respectively applied as a gate. It is composed of a MOS transistor MP4 and a second NMOS transistor MN2 connected with the reset zero signal Rst0 to a gate and connected between the second node N2 and the ground voltage terminal Vss. .

The coupling noise controller 1200 includes a third NMOS transistor MN3 having a gate connected to the second node N2 and connected between the first node N1 and the ground voltage terminal Vss. The fourth NMOS transistor MN4 is connected to the first node N1 and is connected between the second node N2 and the ground voltage terminal Vss.

The latch device 1300 includes a first inverter IV1 connected between the first node N1 and the second node N3, and a second device connected between the third node N3 and the first node N1. The fourth inverter connected between the inverter IV2, the third inverter IV3 connected between the second node N2 and the fourth node N4, and the fourth node N4 and the second node N2. It consists of inverter IV4.

The output switch device 1400 is provided with an output enable zero signal Oe0 and an inverted signal of the output enable zero signal Oe0 as a gate, respectively, and are connected in parallel between the third node N3 and the data output terminal. The fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 and the inverted signal of the output enable zero signal Oe0 and the output enable zero signal Oe0 are respectively applied to a gate. The fifth NMOS transistor MN6 and the PMOS transistor MP6 connected in parallel between the fourth node N4 and the data output terminal, and the output enable zero signal Oe0 to be inverted. The fifth inverter IV5 outputs to the PMOS transistor MP5 and the sixth PMOS transistor MP6 gate terminal.

Referring to the operation in relation to the present invention, when high data is input, the first node N1 is " high " and the second node N2 is " low " It will cause malfunction.

Accordingly, in order to prevent this, the coupling noise control device operates, but even when the first node N2 is "high", the fourth NMOS transistor MN4 is turned on to apply the potential on the second node N2. Passing to " low " prevents malfunction of data due to coupling noise.

In the third exemplary embodiment, the input switch device 2100 receives the high data pulse signal DH and the low data pulse signal DL and outputs a predetermined data signal to the first node N1 and the second node N2. And a coupling noise control device 2200 for controlling the potentials on the first and second nodes N2 and a data signal on the first and second nodes N1 and N2 for a predetermined time. Afterwards, the latch device 2300 outputs a data signal to the third node N3 and the fourth node N4 and the output enable zero signal Oe0, respectively, to operate the third and fourth nodes N4. It is composed of an output switch device 2400 for transmitting a data signal on the data output stage.

The input switch device 2100 is connected in series between a power supply voltage terminal Vcc and the first node N1, and includes a first input signal for inputting a high data pulse signal DH and an input enable zero signal En0 to a gate, respectively. The first NMOS transistor MN1 is connected to the first node N1 and the ground voltage terminal Vss by applying a second PMOS transistor MP2 and a reset zero signal Rst0 to the gate. And third and fourth blood terminals connected in series between a power supply voltage terminal Vcc and the second node N2 and to which a low data pulse signal DL and the input enable zero signal En0 are respectively applied as gates. It is composed of a MOS transistor MP4 and a second NMOS transistor MN2 connected with the reset zero signal Rst0 to a gate and connected between the second node N2 and the ground voltage terminal Vss. .

The coupling noise controller 2200 includes a fifth PMOS having a gate connected to the second node N2 and connected between the power supply voltage terminal Vcc and the source terminal of the first PMOS transistor MP1 of the input switch device. A fifth PMOS transistor having a transistor MP5 and a gate connected to a first node N1 and connected between a power supply voltage terminal Vcc and a source terminal of a third PMOS transistor MP3 of the input switch device; And a sixth PMOS transistor MP6 connected to a first node N1 and connected between a power supply voltage terminal Vcc and a source terminal of the third PMOS transistor MP3 of the input switch device. It is composed of

The latch device 2300 includes a first inverter IV1 connected between the first node N1 and a third node N3, and a second device connected between the third node N3 and the first node N1. Third inverter IV3 connected between inverter IV2, second node N2, and fourth node N4, and fourth inverter connected between fourth node N4 and second node N2. (IV4).

The output switch device 2400 is provided with an output enable zero signal Oe0 and an inverted signal of the output enable zero signal Oe0 as a gate, respectively, and are connected in parallel between the third node N3 and the data output terminal. The third NMOS transistor MN3 and the seventh PMOS transistor MP7 and a gate inverted signal of the output enable zero signal Oe0 and the output enable zero signal Oe0 are respectively applied to the gate. The fourth NMOS transistor MN4 and the eighth PMOS transistor MP8 and the output enable zero signal Oe0 that are connected in parallel between the fourth node N4 and the data output terminal are inverted. And a fifth inverter IV5 output to the gate terminal of the PMOS transistor MP7 and the eighth PMOS transistor MP8.

Referring to the operation thereof, when high data is input, the first node N1 and the second node N2 are equally "low" in the first standby state, and thus the "low" potential on the second node N2. As a result, the fifth PMOS transistor MP5 is turned on so that the first node N1 becomes “high”.

On the other hand, even when the third PMOS transistor MP3 of the input switch device is turned on due to the coupling noise, the sixth PMOS transistor MP6 connected by the first node N1 to control the power supply voltage. The second node N2 that is turned off may not have a "high" and maintains a "low" level as in the normal state.

As described above in the first, second, and third embodiments, when a malfunction occurs in the pipe register due to the coupling noise generated in the data line, the latch device, the second, and the third embodiment in the first embodiment. It can be seen that the coupling noise device of the embodiment prevents the pipe resistor from malfunctioning by controlling the potential rise due to the noise.

As described above, when the present invention is applied to a pipeline of a semiconductor device, even if a noise signal is input to a dynamic pulse data signal input to a pipe resistor circuit configured in parallel, a malfunction does not occur.

The present invention is applied to a product having a lifeline, such as a synchronous DRAM as a device that can effectively filter noise.

Preferred embodiments of the present invention are for purposes of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (6)

In a pipeline apparatus that delivers data signals sequentially generated by an external synchronization signal, the pipeline apparatus operates by a predetermined data pulse signal in a standby state to generate potentials of the same level at the first node and the second node, and in an active state. An input switching means for operating the first node and the second node to generate an opposite level potential by a predetermined data pulse signal at a time; and between the first and second nodes and the third and fourth nodes, Latching means for preventing the occurrence of the same data by controlling abnormal potential on the first or second node after latching data on the first or second node for a predetermined time, and between the third and fourth nodes and the data output terminal. And an output switching means connected to output data on the third and fourth nodes. The pipeline device of claim 1, wherein the latch means comprises flip-flop logic. The NAND gate of claim 1, wherein the latch unit comprises: a first NAND gate having one input terminal connected to the first node, another input terminal connected to the fourth node, and an output terminal connected to the third node; A second NAND gate connected to a second node, the other input terminal is connected to the third node, and an output terminal is connected to the fourth node, and a first phosphor which inverts the potential on the third node to output to the first node. And a second inverter for inverting a potential on the fourth node and outputting the inverted voltage to the second node. In a pipeline apparatus for transmitting data signals sequentially generated by an external synchronization signal, the pipeline apparatus operates by a predetermined data pulse signal in a standby state to generate potentials of the same level at the first node and the second node in an active state. Input switching means for generating opposite level potentials to the first node and the second node by operating a predetermined data pulse signal, and connected to an output terminal of the input switching means, the first or the second according to coupling noise. Coupling noise control means for controlling abnormal data on a node, latch means connected between the first and second nodes and third and fourth nodes to latch data on the first or second node for a predetermined time; An output switching number connected between the third and fourth nodes and a data output terminal to output data on the third and fourth nodes; A pipeline device of a semiconductor device, characterized in that it comprises a stage. The method of claim 4, wherein the coupling noise control means comprises: a first MOS transistor having a gate connected to the second node, and connected between the first node and a ground voltage terminal; and a gate connected to the first node; And a second MOS transistor connected between the second node and the ground voltage terminal. 5. The method of claim 4, wherein the coupling noise control means comprises: a third MOS transistor having a gate connected to the second node and a power supply voltage terminal and the input switching means; And a fourth MOS transistor connected between a power supply voltage terminal and the input switching means.

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