KR100408865B1 - Control circuit for pipe registor - Google Patents

Abstract

The present invention relates to a pipe register control circuit, comprising: transfer means for selectively outputting output data of a first control signal or a data bus sense amplifier in accordance with a DQ compression test signal and an inverted signal thereof, an output signal of the transfer means, Logic means for logically combining the inverted signal and the read signal of the second control signal, and counting means for sequentially outputting a plurality of pipe register control signals in accordance with the read signal and the output signal of the logic means, In the normal operation, the pipe register control signal is output in synchronization with the first control signal. In the DQ compression test mode, the pipe register control signal is output in synchronization with the output data of the data bus sense amplifier. Preventable Pipe Regis A control circuit is provided.

Description

Control circuit for pipe registor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipe register control circuit, wherein in normal operation, a pipe register control signal is output in synchronization with a control signal, and in the DQ compression test mode, a pipe register control signal is output in synchronization with read data to malfunction. It relates to a pipe register control circuit that can be prevented from becoming.

FIG. 1 is a block diagram schematically illustrating a conventional pipe resistor and a peripheral circuit for driving the same. A configuration thereof is as follows.

The first DQ compress multiplexer 11 inputs first read data grd <0> and its inverted data grdb <0> output from a data bus sense amplifier. The first output data dout <0> and its inverted data doubt <0> are output. The second DQ compression multiplexer 12 inputs the second read data grd <1> and its inverted data grdb <1> output from the data bus sense amplifier, and the second output data dout <1>. And its inversion data (doutb <1>). The third DQ compression multiplexer 13 inputs the third read data grd <2> and its inverted data grdb <2> output from the data bus sense amplifier, and the third output data dout <2>. And its inverted data doubt <2>. The fourth DQ compression multiplexer 14 includes first to fourth read data grd <0,1,2,3> and its inversion data (grdb <0,1,2,3>) output from the data bus sense amplifier. ), And outputs the fourth output data dout <3> and its inverted data doubt <3> according to the special test signal DQ compression mode test signal stm_dqc. The output data dout is kept low when the output data of the data bus sense amplifier is high, and the inverted output data doubt is kept low when the output data of the data bus sense amplifier is low. . The pipe register control circuit 15 inputs the fourth output data dout <3> and its inverted data doubt <3> outputted from the fourth DQ compression multiplexer 14, and outputs the first output data dout <3> according to the control signal pcd_t. The first to third pipe register control signals pcd <0,1,2> are output. The first to third pipe registers 16 to 18 commonly input the fourth output data dout <3> and the inverted data dodoutb <3>, which are output signals of the fourth DQ compression multiplexer 14. , The first to third pipe register control signals pcd <0,1,2> and the pipe register count signal pcnt <0,1,2>, respectively, to input pull-up signals pu and pull-down signals pd. Output sequentially.

In the above configuration, the first to third DQ compression multiplexers 11 to 13 may include first to third read data grd <0,1 and 2> and its inverted data <grdb <0,1 and 2>. And transmits the first to third output data dout <0,1,2> and the inverted data doubt <0,1,2>. However, the fourth DQ compression multiplexer 14 determines its operation according to the DQ compression mode test signal stm_dqc. When the DQ compression mode test signal stm_dqc is input in a low state, that is, in the normal mode, the fourth DQ compression multiplexer 14 The fourth output data dout <3> is output by acting as a transfer gate that transfers the read data grd <3>. However, when the DQ compression mode test signal stm_dqc is applied in the high state, that is, in the DQ compression test mode, the fourth DQ compression multiplexer 14 functions as a multiplexer, and the first to fourth read data grd <0, 1,2,3>) determines the output data. That is, when all of the first to fourth read data grd <0,1,2,3> are the same, the data is output, and the first to fourth read data grd <0,1,2,3> are output. If is not the same, all of the fourth output data dout <3> and its inverted data doubt <3> are output in a low state.

However, as described above, the fourth DQ compression multiplexer 14 functions as a transmission gate when operating in the normal mode and as a multiplexer when operating in the DQ compression test mode, and thus the fourth output data dout <3>. ) Is output in the DQ compression test mode with a delay in normal operation. In this case, as shown in the waveform diagram of FIG. 2, in the DQ compression test mode, the pipe register control circuit 15 transmits the fourth output data dout <3> to the second pipe register control signal pcd <1>. The synchronous output causes the pipe registers to malfunction.

An object of the present invention is to output the pipe register control signal in synchronization with the control signal (pcd_t) in normal operation, and to output the pipe register control signal in synchronization with the read data in the DQ compression test mode to prevent the pipe register from malfunctioning To provide a pipe register control circuit that can be.

1 is a block diagram schematically illustrating a conventional pipe resistor and a peripheral circuit for driving the same.

2 is an output waveform diagram of a conventional pipe resistor control circuit.

3 is a block diagram schematically illustrating a pipe resistor and a peripheral circuit for driving the same according to the present invention;

4 is a pipe register control circuit diagram in accordance with the present invention.

5 is an output waveform diagram of a pipe register control circuit according to the present invention;

<Explanation of symbols for the main parts of the drawings>

21 to 24: first to fourth DQ compression multiplexers

25: pipe resistor control circuit

26 to 28: first to third pipe resistor

The pipe register control circuit according to the present invention includes transfer means for selectively outputting output data of a first control signal or a data bus sense amplifier in accordance with a DQ compression test signal and an inverted signal thereof, an output signal of the transfer means, and a second signal. Logic means for logically combining the inverted signal and the read signal of the control signal; and counting means for sequentially outputting the first to third pipe register control signals in accordance with the read signal and the output signal of the logic means. It is characterized by.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram schematically illustrating a pipe resistor and a peripheral circuit for driving the same according to the present invention.

The first DQ compress multiplexer 21 inputs first read data grd <0> and its inverted data grdb <0> output from the data bus sense amplifier, and inputs the first output data ( dout <0> and its inversion data (doutb <0>) are output. The second DQ compression multiplexer 22 inputs the second read data grd <1> and its inverted data grdb <1> output from the data bus sense amplifier, and the second output data dout <1>. And its inversion data (doutb <1>). The third DQ compression multiplexer 23 inputs the third read data grd <2> and its inverted data grdb <2> output from the data bus sense amplifier, and the third output data dout <2>. And its inverted data doubt <2>. The fourth DQ compression multiplexer 24 includes first to fourth read data grd <0,1,2,3> and its inverted data grdb <0,1,2,3> output from the data bus sense amplifier. ), And outputs the fourth output data dout <3> and its inverted data doubt <3> according to the special test signal DQ compression mode test signal stm_dqc. Here, the output data dout is kept low when the output data of the data bus sense amplifier is high, and the inverted output data doubt is kept low when the output data of the data bus sense amplifier is low. do. The pipe register control circuit 25 inputs the fourth output data dout <3> and its inversion data dodoutb <3> output from the fourth DQ compression multiplexer 24, and unlike the conventional method, the control signal pcd_t And the first to third pipe register control signals pcd <0,1,2> according to the DQ compression mode test signal stm_dqc. The first to third pipe registers 26 to 28 commonly input fourth output data dout <3> and its inverted data doubt <3>, which are output signals of the fourth DQ compression multiplexer 24, , The first to third pipe register control signals pcd <0,1,2> and the pipe register count signal pcnt <0,1,2>, respectively, to input pull-up signals pu and pull-down signals pd. Output sequentially.

In the above configuration, the first to third DQ compression multiplexers 21 to 23 may include first to third read data grd <0,1 and 2> and its inverted data <grdb <0,1 and 2>. And transmits the first to third output data dout <0,1,2> and the inverted data doubt <0,1,2>. However, the fourth DQ compression multiplexer 24 determines its operation according to the DQ compression mode test signal stm_dqc. When the DQ compression mode test signal stm_dqc is input in the low state, that is, in the normal mode, the fourth DQ compression multiplexer 24 determines the operation. The fourth output data dout <3> is output by acting as a transfer gate that transfers the read data grd <3>. However, when the DQ compression mode test signal stm_dqc is applied in the high state, that is, in the DQ compression test mode, the fourth DQ compression multiplexer 24 acts as a multiplexer, and the first to fourth read data grd <0, 1,2,3>) determines the output data. That is, when all of the first to fourth read data grd <0,1,2,3> are the same, the data is output, and the first to fourth read data grd <0,1,2,3> are output. If is not the same, all of the fourth output data dout <3> and its inverted data doubt <3> are output in a low state.

Meanwhile, since the pipe register control circuit 25 according to the present invention operates according to the control signal pcd_t and the DQ compression mode test signal stm_dqc, the pipe register control signal is synchronized with the control signal pcd_t during normal operation. In the DQ compression test mode, the pipe register control signal is synchronized with the read data to prevent the pipe register from malfunctioning.

4 is a circuit register control circuit diagram according to the present invention, and is configured as follows.

The first transfer gate T31 is driven by the PMOS side according to the special test mode DQ compression test signal stm_dqc, and the NMOS side according to the signal in which the DQ compression test signal stm_dqc is inverted through the first inverter I31. The driving signal pcd_t transfers the inverted signal through the second inverter I32. The first NAND gate 31 inputs and logically combines the third read data dout <3> and its inverted data doubt <3>. The second transfer gate T32 is driven by the NMOS side according to the DQ compression test signal stm_dqc, and the PMOS side is driven according to the signal inverted by the DQ compression test signal stm_dqc through the first inverter I31. 1 The output signal of the NAND gate 31 is transferred. The second NAND gate 32 may be a signal in which a cas latency 1 (ca1) signal is inverted through the third inverter I33 and a signal transmitted through the first or second transmission gate T31 or T32, The read signal read inputs the delayed signals through the fourth and fifth inverters I34 and I35 and logically combines them. On the other hand, the read signal read delayed through the fourth and fifth inverters I34 and I35 becomes the potential of the first node Q31, and the output signal of the second NAND gate 32 is the second node ( It becomes the potential of Q32). The third NAND gate 33 inputs the logic of the potential of the first node Q31 and the output signal of the third transfer gate T33 or the seventh inverter I37. The third transfer gate T33 has a PMOS side driven according to the potential of the second node Q32, and the NMOS side has a potential in which the potential of the second node Q22 is inverted through the sixth inverter I36. It is driven according to the potential of the three nodes Q33 to transfer the potential of the fourth node Q34. The seventh inverter I37 inverts the output signal of the third NAND gate 33 and inputs it to one of the input terminals of the third NAND gate 33. The fourth transfer gate T34 in which the NMOS side is driven according to the potential of the second node Q32 and the PMOS side is driven in accordance with the potential of the third node Q33 receives the output signal of the third NAND gate 33. The output signal of the eighth inverter I38 to be inverted is transferred. The first latch means 34 composed of the ninth and tenth inverters I39 and I40 latches data transferred through the fourth transfer gate T34. The eleventh inverter I41 inverts the output signal of the first latch means 34, the PMOS side is driven according to the potential of the second node Q32, and the NMOS side is driven according to the potential of the third node Q33. The driven fifth transmission gate T35 transfers the output signal of the eleventh inverter I41. The fifth NAND gate 35 inputs and logically combines the potential of the first node Q31 and the output signal of the fifth transfer gate T35 or the twelfth inverter I42. The twelfth inverter I42 inverts the output signal of the fifth NAND gate 35 and inputs it to one input terminal of the fifth NAND gate 35. The sixth transfer gate T36 having the NMOS side driven according to the potential of the second node Q32 and the PMOS side driven according to the potential of the third node Q33 receives the output signal of the fifth NAND gate 35. The output signal of the thirteenth inverter I43 to be inverted is transferred. The second latch means 36 composed of the fourteenth and fifteenth inverters I44 and I45 latches the data transferred through the sixth transfer gate T36. The sixteenth inverter I46 inverts the output signal of the second latch means 36, the PMOS side is driven according to the potential of the second node Q32, and the NMOS side is driven according to the potential of the third node Q33. The seventh transmission gate T37 that is driven transfers the output signal of the sixteenth inverter I46. The first NOR gate 37 outputs an output signal of the seventeenth inverter I47 and an output signal of the seventh transmission gate T37 or an output signal of the eighteenth inverter I48 that inverts the potential of the first node Q31. And logically combine them. The eighteenth inverter I48 inverts the output signal of the first NOR gate 37 and inputs it to one input terminal of the first NOR gate 37. The eighth transfer gate T38, in which the NMOS side is driven according to the potential of the second node Q32 and the PMOS side is driven according to the potential of the third node Q33, receives the output signal of the first NOR gate 37. The output signal of the nineteenth inverter I49 to invert is transferred. The third latch means 38 including the twentieth and twenty-first inverters I50 and I51 latches the data transferred through the eighth transfer gate T38. The 22nd inverter I52 inverts the output signal of the 3rd latch means 38, and the output signal of the 22nd inverter I52 becomes the electric potential of the 4th node Q34. The fifth NAND gate 39 inputs the potential of the fourth node Q34 and the potential of the first node Q31 and logically combines them. The twenty-third and twenty-fourth inverters I53 and I54 delay the output signal of the fifth NAND gate 39 to output the first pipe register control signal pcd <0>. The sixth NAND gate 50 inputs the output signal of the eleventh inverter I41 and the potential of the first node Q31, and logically combines them. The 25th and 26th inverters I55 and I56 delay the output signal of the sixth NAND gate 50 to output the second pipe register control signal pcd <1>. The seventh NAND gate 51 inputs the output signal of the sixteenth inverter I46 and the potential of the first node Q31, and logically combines them. The 27th and 28th inverters I57 and I58 delay the output signal of the seventh NAND gate 51 to output the third pipe register control signal pcd <2>.

The driving method of the pipe resistor control circuit according to the present invention configured as described above will be described with reference to the output waveform diagram of FIG. 5.

In the initial state, the special test mode DQ compression test signal stm_dqc, the control signal pcd_t, and the read signal read are applied in the low state. The cas latency 1 (cl1) is applied to the low state because it is a signal for outputting the pipe register control signal pcd only when the cas latencys 2 and 3 are used. Then, the fourth output data dout <3> and its inverted data doubt <3> are applied from the fourth DQ compressed multiplex. The cas latency 1 ca1 in the low state is inverted to the high state through the third inverter I33 and input to the second NAND gate 32. The first transfer gate T31 is turned on by the DQ compression test signal stm_dq applied to the low state and the signal in which the signal is inverted to the high state through the first inverter I31, and the second transfer gate T32 is turned on. Is turned off. Therefore, the control signal pcd_t in the low state is inverted to the high state through the second inverter I32 and input to the second NAND gate 32 through the turned-on first transfer gate T31. In addition, the read signal read in the low state is delayed through the fourth and fifth inverters I34 and I35 and input to the second NAND gate 32. On the other hand, since the output signal of the fifth inverter I35 becomes the potential of the first node Q31, the first node Q31 maintains the potential of the low state. The second NAND gate 32 inputs the three signals and logically combines them to output a high state signal. The second node Q32 is kept high by the output signal of the second NAND gate 32. The potentials of the second node Q32 and the potential of the second node Q32 that maintain the high state are changed by the potential of the third node Q33 in which the potential of the second node Q32 is inverted to the low state through the sixth inverter I36. The sixth and eighth transfer gates T34, T36, and T38 are turned on, and the fifth, seventh, and ninth transfer gates T35, T37, and T39 are turned off. The third NAND gate 33 for inputting the output signal of the seventh inverter I37 for inverting the potential of the first node Q31 and the output signal of the third NAND gate 33 to maintain the low state is in a high state. Output the signal. The output signal of the third NAND gate 33 that maintains the high state is inverted to the low state through the eighth inverter I38, transferred through the fourth transfer gate T34, and latched to the first latch means 34. do. The data latched by the first latch means 34 is inverted to a low state by the eleventh inverter I41 and outputted, but cannot be transferred to the next stage because the fifth transfer gate T35 is turned off. The output signal of the eleventh inverter I41 is input to one input terminal of the sixth NAND gate 50 as the second output signal out <1>. The fourth NAND gate 35 that inputs the output signal of the twelfth inverter I42 that inverts the potential of the first node Q31 that maintains the low state and the output signal of the fourth NAND gate 35 is in a high state. Output the signal. The output signal of the fourth NAND gate 35 which maintains the high state is inverted to the low state through the thirteenth inverter I43, transferred through the sixth transfer gate T36, and latched by the second latch means 36. do. The data latched in the first latch means 36 is inverted and outputted in the low state by the sixteenth inverter I46, but cannot be transferred to the next stage because the seventh transfer gate T37 is turned off. The output signal of the sixteenth inverter I46 is input to one input terminal of the seventh NAND gate 51 as the third output signal out <2>. The potential of the first node Q31 maintaining the low state is inverted to the high state through the seventeenth inverter I47 and input to the first NOR gate 37. The first NOR gate 37 receives a low state by inputting an output signal of the seventeenth inverter I47 that is input in a high state and an output signal of the eighteenth inverter I48 that inverts the output signal of the first NOR gate 37. Outputs the signal of. The output signal of the first NOR gate 37 output in the low state is inverted to the high state through the nineteenth inverter I49 and latched by the third latch means 38 through the eighth transfer gate T38. The data latched in the third latch means 38 is inverted to the high state through the twenty-second inverter I52. The output signal of the twenty-second inverter I52 becomes the potential of the fourth node Q34 and is input to one input terminal of the fifth NAND gate 49 as the first output signal out <0>. A potential of the first output signal out <0> that maintains the high state and the potential of the first node Q31 that maintains the low state is input from the fifth NAND gate 49 and logically combined to output a high state signal. . The output signal of the fifth NAND gate 49 output in the high state is delayed through the twenty-third and twenty-fourth inverters I53 and I54 and output as the first pipe register control signal pcd <0> in the high state. A second output signal out <1> that maintains a low state and a potential of the first node Q31 that maintains a low state are input from the sixth NAND gate 50 and logically combined to output a high state signal. . The output signal of the sixth NAND gate 50 output in the high state is delayed through the 25th and 26th inverters I55 and I56 and output as the second pipe register control signal pcd <1> in the high state. On the other hand, the potential of the third output signal out <2> that maintains the low state and the potential of the first node Q31 that maintains the low state is input from the seventh NAND gate 51 and logically combined to provide a high state signal. Output The output signal of the seventh NAND gate 51 output in the high state is delayed through the 27th and 28th inverters I57 and I58 and output as the third pipe register control signal pcd <2> in the high state.

In the normal operation, the special test mode DQ compression test signal stm_dq is applied in a low state, and the control signal pcd_t is applied in a pulse of repeating a low or high state. The read signal read is applied in a high state. In addition, cas latency 1 (cl1) is applied in a low state, and the fourth output data dout <3> and its inverted data doubt <3> from the fourth DQ compression multiplexer are input. The cas latency 1 ca1 in the low state is inverted to the high state through the third inverter I33 and input to the second NAND gate 32. The first transfer gate T31 is turned on by the DQ compression test signal stm_dq applied to the low state and the signal in which the signal is inverted to the high state through the first inverter I31, and the second transfer gate T32 is turned on. Is turned off. Accordingly, the low or high control signal pcd_t is inverted to a high or low state through the second inverter I32 and input to the second NAND gate 32 through the turned-on first transfer gate T31. . In addition, the read signal read in the high state is delayed through the fourth and fifth inverters I34 and I35 and input to the second NAND gate 32. On the other hand, since the output signal of the fifth inverter I35 becomes the potential of the first node Q31, the first node Q31 maintains the potential of the high state. The second NAND gate 32 inputs the three signals and logically combines them to output a low or high state signal. The second node Q32 is kept low or high by the output signal of the second NAND gate 32. First, an operation in which the second node Q32 is kept low will be described below. same. The potentials of the second node Q32 and the potential of the second node Q32 that maintain the low state are changed by the potential of the third node Q33 that is inverted to the high state through the sixth inverter I36. The sixth and eighth transfer gates T34, T36, and T38 are turned off, and the fifth, seventh, and ninth transfer gates T35, T37, and T39 are turned on. The third NAND gate 33 for inputting the potential of the first node Q31 that maintains the high state and the potential of the fourth node Q34 that is input through the third transfer gate T33 outputs a low state signal. do. The output signal of the third NAND gate 33 maintaining the low state is inverted to a high state through the seventh inverter I37 and re-input to one input terminal of the third NAND gate 33. Accordingly, the third NAND gate 33 outputs a signal in a low state, and this output signal is inverted to a high state through the eighth inverter I38, but because the fourth transfer gate T34 is turned off, the next It is not delivered to the stage. Accordingly, the first latch means 34 latches previous data to output a high state signal, and is inverted through the eleventh inverter I41 to output a low state signal. The output signal of the eleventh inverter I41 is input to one input terminal of the sixth NAND gate 50 as the second output signal out <1>. The fourth NAND gate 35 that inputs the potential of the first node Q31 that maintains the high state and the output signal of the eleventh inverter I41 that maintains the low state input through the fifth transfer gate T35 Outputs the signal in the high state. The output signal of the fourth NAND gate 35 that maintains the high state is inverted to the low state through the twelfth inverter I42 and re-entered into one input terminal of the fourth NAND gate 35 so that the fourth NAND gate 35 ) Outputs a high state signal. The output signal of the fourth NAND gate 35 maintaining the high state is inverted to the low state through the thirteenth inverter I43, but cannot be transferred to the next stage because the sixth transfer gate T36 is turned off. Accordingly, the second latch means 36 latches previous data and outputs a high state signal, and is inverted to a low state by the sixteenth inverter I46 and output. The output signal of the sixteenth inverter I46 is input to one input terminal of the seventh NAND gate 51 as the third output signal out <2>. The potential of the first node Q31 maintaining the high state is inverted to the low state through the seventeenth inverter I47 and input to the first NOR gate 37. The first NOR gate 37 inputs the output signal of the seventeenth inverter I47 keeping the low state and the output signal of the sixteenth inverter I46 keeping the low state through the seventh transmission gate T37 to thereby make the first NOR gate 37 high. Output the status signal. The output signal of the first NOR gate 37 which maintains the high state is inverted to the low state by the eighteenth inverter I48 and is input to one input terminal of the first NOR gate 37 so that the first NOR gate 37 Outputs a high state signal. The output signal of the first NOR gate 37 output in the high state is inverted to the low state through the nineteenth inverter I49, but data cannot be transferred to the next stage because the eighth transfer gate T38 is turned off. . Accordingly, the third latch means 38 latches previous data to output the low data, and is inverted to the high state through the twenty-second inverter I52. The output signal of the twenty-second inverter I52 becomes the potential of the fourth node Q34 and is input to one input terminal of the third NAND gate 33 through the third transfer gate T33 and simultaneously with the first output signal. It is input to one input terminal of the fifth NAND gate 49 as (out <0>). A potential of the first output signal out <0> that maintains the high state and the potential of the first node Q31 that maintains the high state is input from the fifth NAND gate 49 and logically combined to output a low state signal. . The output signal of the fifth NAND gate 49 output in the low state is delayed through the twenty-third and twenty-fourth inverters I53 and I54 and output as the first pipe register control signal pcd <0> in the low state. A second output signal out <1> that maintains a low state and a potential of the first node Q31 that maintains a high state are input from the sixth NAND gate 50 and logically combined to output a high state signal. . The output signal of the sixth NAND gate 50 output in the high state is delayed through the 25th and 26th inverters I55 and I56 and output as the second pipe register control signal pcd <1> in the high state. On the other hand, the potential of the third output signal out <2> that maintains the low state and the first node Q31 that maintains the high state is input from the seventh NAND gate 51 and logically combined to provide a high state signal. Output The output signal of the seventh NAND gate 51 output in the high state is delayed through the 27th and 28th inverters I57 and I58 and output as the third pipe register control signal pcd <2> in the high state.

The operation in the case where the control signal pcd_t transitions to the high state and the second NAND gate 32 outputs a high state signal and thus the second node Q32 is maintained in the high state will be described below. same. The potentials of the second node Q32 and the potential of the second node Q32 that maintain the high state are changed by the potential of the third node Q33 in which the potential of the second node Q32 is inverted to the low state through the sixth inverter I36. The sixth and eighth transfer gates T34, T36, and T38 are turned on, and the fifth, seventh, and ninth transfer gates T35, T37, and T39 are turned off. The third NAND gate 33 which re-inputs the potential of the first node Q31 holding the high state and its output again outputs a low state signal. The output signal of the third NAND gate 33 maintaining the low state is inverted to a high state through the seventh inverter I37 and re-input to one input terminal of the third NAND gate 33. Accordingly, the third NAND gate 33 outputs a signal in a low state, which is inverted to a high state through the eighth inverter I38. The output signal of the eighth inverter I38 is latched to the first latch means 34 via the turned on fourth transfer gate T34. The data latched in the first latch means 34 is inverted to a high state through the eleventh inverter I41, and this signal is the second output signal out <1>, which is one of the sixth NAND gates 50. It is input to the input terminal of. On the other hand, the output signal of the eleventh inverter I41 is not transmitted to the next stage because the fifth transfer gate T35 is turned off. The fourth NAND gate 35 which re-inputs the potential of the first node Q31 holding the high state and its output signal outputs a low state signal. The output signal of the fourth NAND gate 35 maintaining the low state is inverted to a high state through the twelfth inverter I42 and re-entered into one input terminal of the fourth NAND gate 35, so that the fourth NAND gate 35 ) Outputs a low state signal. The output signal of the fourth NAND gate 35 maintaining the low state is inverted to the high state through the thirteenth inverter I43, and latched by the second latch means 36 through the sixth transfer gate T36. The data latched in the second latch means 36 is inverted to a high state through the sixteenth inverter I46, and this signal is the third output data dout <2>, which is one of the seventh NAND gates 51. It is input to the input terminal of. However, since the third output signal out <2> is the next counting signal of the second output signal out <1>, the third output signal out <2> has a predetermined time difference. On the other hand, since the seventh transmission gate T37 maintains the turn-off state, the output signal of the sixteenth inverter I46 may not be transmitted to the next stage. The potential of the first node Q31 maintaining the high state is inverted to the low state through the seventeenth inverter I47 and input to the first NOR gate 37. The first NOR gate 37 inputs the output signal of the seventeenth inverter I47 maintaining the low state to output a high state signal, and the high state output signal is brought low through the 28th inverter I48. Since the inverted signal is input again, a high state signal is output. The output signal of the first NOR gate 37 in the high state is inverted to the low state through the 29th inverter I49, and this signal is latched to the third latching means 38 through the eighth transfer gate T38. . The data latched in the third latch means 38 is inverted to a low state through the thirty-second inverter I52, and the potential of this signal becomes the potential of the fourth node Q34 and at the same time the first output signal out <0. >), It is input to one input terminal of the fifth NAND gate 49. A potential of the first output signal out <0> that maintains the low state and the first node Q31 that maintains the high state is input from the fifth NAND gate 49 and logically combined to output a high state signal. . The output signal of the fifth NAND gate 49 output in the high state is delayed through the twenty-third and twenty-fourth inverters I53 and I54 and output as the first pipe register control signal pcd <0> in the high state. A second output signal out <1> that maintains a high state and a potential of the first node Q31 that maintains a high state are input from the sixth NAND gate 50 and logically combined to output a low state signal. . The output signal of the sixth NAND gate 50 output in the low state is delayed through the 25th and 26th inverters I55 and I56 and output as the second pipe register control signal pcd <1> in the low state. On the other hand, the potential of the third output signal out <2> that maintains the low state and the first node Q31 that maintains the high state is input from the seventh NAND gate 51 and logically combined to provide a high state signal. Output The output signal of the seventh NAND gate 51 output in the high state is delayed through the 27th and 28th inverters I57 and I58 and output as the third pipe register control signal pcd <2> in the high state.

When performing the special test mode DQ compression test operation, the special test mode DQ compression test signal stm_dq is applied in a high state, and the control signal pcd_t is applied as a pulse which repeats the low and high states, and the read signal ( read) is applied in a high state. In addition, the cascade latency 1 cl1 is applied in a low state, and the fourth output data dout <3> and its inverted data doubt <3> are input from the fourth DQ compression multiplexer. The fourth output data dout <3> is input in a low state when the output of the data bus sense amplifier is in a high state, and the inverted data (doutb <3>) is input when the output of the data sense amplifier is in a low state. It is entered low. Thus, the output signal of the first NAND gate 31 remains high. The cas latency 1 ca1 in the low state is inverted to the high state through the third inverter I33 and input to the second NAND gate 32. The first transfer gate T31 is turned off by the DQ compression test signal stm_dq applied to the high state and the signal in which the signal is inverted to the high state through the first inverter I31, and the second transfer gate T32 is turned off. ) Is turned on. Therefore, the output of the high state of the first NAND gate 31 which logically combines the fourth read data (dout <3>) and its inverted data (doutb <3>) through the turned-on second transfer gate T31. The signal is input to the second NAND gate 32. In addition, a high read signal read is delayed through the fourth and fifth inverters I34 and I35 and input to the second NAND gate 32. On the other hand, since the output signal of the fifth inverter I35 becomes the potential of the first node Q31, the first node Q31 maintains the potential of the high state, and the second NAND gate 32 supplies the three signals. The signal is outputted in a low state by inputting and logically combining the same, and thus, the operation in the normal mode as described above and the same operation as in the case where the control signal pcd_t is applied in the low state will not be described in detail. do.

As described above, according to the present invention, when the pipe register control circuit operates in the normal mode, the pipe register control signal is synchronized with the control signal pcd_t, and when the pipe register control circuit operates in the DQ compression mode, the pipe register control signal is outputted from the data bus sense amplifier. By synchronizing with the data, the pipe register can be prevented from malfunctioning, thereby improving reliability.

Claims (7)

Transfer means for selectively outputting output data of the first control signal or data bus sense amplifier in accordance with the test signal and its inverted signal; Logic means for logically combining the output signal of the transfer means, the inverted signal of the second control signal and the read signal; And counting means for sequentially outputting a plurality of pipe register control signals in accordance with the read signal and the output signal of the logic means. 2. The transfer device of claim 1, wherein the transfer unit comprises: a first transfer gate configured to drive a PMOS transistor according to the test signal and to drive an NMOS transistor according to an inverted signal of the test signal to output the first control signal; And a second transfer gate configured to drive an NMOS transistor according to the test signal and to output an output data of the data bus sense amplifier by driving the PMOS transistor according to the inverted signal of the test signal. Control circuit. The pipe register control circuit according to claim 1, wherein said logic means is a NAND gate. 2. The apparatus of claim 1, wherein the counting means comprises: a plurality of transmission gates driven in accordance with an output signal of the logic means and an inverted signal thereof; A plurality of first logic means connected between the transfer gates and for logically combining the read signal and the signal input through the transfer gate; A plurality of latch means connected between said transfer gates for latching an output signal of said logic means; And a plurality of second logic means for logically combining the output signal of each of said plurality of latch means and said read signal to output a plurality of pipe register control signals. 5. The plurality of transfer gates of claim 4, wherein the plurality of transfer gates include a transfer gate in which a PMOS transistor is driven according to an output signal of the logic means, and an NMOS transistor is driven in accordance with an inversion signal of the output signal of the logic means. And a transfer gate in which an NMOS transistor is driven in accordance with an output signal, and a transfer gate in which the PMOS transistor is driven in accordance with an inverted signal of the output signal of the logic means. 5. The apparatus of claim 4, wherein the first logic means comprises: a plurality of NAND gates connected between alternating transfer gates for logical combination of the read signal and the output signal of the latch circuit input through the transfer gate; And a NOR gate connected between the alternating plurality of transfer gates to logically combine an inverted signal of the read signal and an output signal of the latch circuit input through the transfer gate. 5. The pipe register control circuit according to claim 4, wherein said second logic means is a NAND gate.