KR100517909B1 - Semiconductor device - Google Patents

Abstract

The present invention is to provide a semiconductor device for controlling the input buffer so that the external signal is transferred to the semiconductor after all input signals are stabilized in the initial operation mode when the power is first applied to the semiconductor device. The present invention provides a plurality of normal input buffers each buffering a plurality of external signals and transferring the same to a inside of a semiconductor device; A clock enable buffer for receiving a clock enable command compared to a reference signal and outputting the clock enable command as a clock enable signal; A power-up mode input buffer that is enabled by a power-up signal, outputs an initial stabilization signal in response to an enable time of the clock enable command, and is disabled in response to a feedback of the initial stabilization signal; And an input buffer enable signal generator configured to enable the initial stabilization signal to generate an input buffer enable signal that receives the clock enable signal and enables the plurality of normal input buffers. do.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a clock enable buffer for controlling a plurality of input buffers that receive various clock signals by receiving a clock enable signal.

A general semiconductor device receives a clock signal from an external source and operates the clock signal as a reference timing of an internal operation. In particular, in a memory device, a synchronous DRAM performs read and write operations of data in synchronization with an external clock signal applied from the outside. For this reason, semiconductor devices such as a synchronous DRAM have a clock buffer for buffering and delivering an external clock signal therein and a clock enable buffer for controlling the clock buffer.

The clock enable buffer latches a clock enable signal input from an external source and outputs the clock enable signal to the clock buffer. The clock buffer is enabled by a signal output from the clock enable buffer to output an internal clock signal into the semiconductor device. do.

In the conventional semiconductor device, since all operations are performed using the internal clock signal as a reference timing, it is very important to accurately operate the clock enable buffer for controlling the clock buffer.

1 is a block diagram showing a semiconductor device according to the prior art.

Referring to FIG. 1, a semiconductor device may include a clock enable buffer 10 and a clock enable buffer 10 that receive a clock enable signal CKE as compared to a reference signal Vref having a predetermined reference potential. The latch unit 20 for latching the output and the clock enable signals cke2 and ckez, which are enabled by the power-up signal pwrup and latched by the latch unit 20, are input. And an input buffer enable signal generator 30 for outputting an input buffer enable signal BE for enabling 16).

1 shows a plurality of input buffers 11 to 16 and various input buffers 11 to 16 that receive various control signals and address signals A1, A0, CS, RAS, CAS, WE ... A plurality of latch portions 21 to 26 are shown for latching the output signals and outputting them into the semiconductor device. The plurality of input buffers 11 to 16 receive one signal of one of various control signals and address signals A1, A0, CS, RAS, CAS, WE ... on one side, and a reference signal Vref input to the other side. Output in comparison with

FIG. 2 is a circuit diagram showing one of the input buffers 11 to 16 shown in FIG.

Referring to FIG. 2, the input buffers 11 to 16 are NMOS transistors MN1 and MN2 that receive the reference signal Vref and the input signal IN as their gates, and the input buffer enable signal BE. ) Is inverted and input to the gate, one side of which is commonly connected to one side of the NMOS transistors (MN1, MN2), and the other side of which has an NMOS transistor (MN3) connected to the ground power supply (VSS), and the power voltage (VDD) and Anne The other side of the MOS transistor MN1 is connected and its gate is connected to the other side of the ANMOS transistor MN1 with the PMOS transistor MP1 connected to the other side of the NMOS transistor MN1, and the other side of the power voltage VDD and the ANMOS transistor MN2. The MOS transistor MP1 and the PMOS transistor MP2 forming the current mirror, and the input buffer enable signal BE inverted to the gate are received, and the other side of the power supply voltage VDD and the MOS transistor MN1 is received. PIM transistor (MP3) for connecting and input buffer enable signal to gate (BE) is inverted and input, and the PMO transistor MP4 connecting the other side of the power supply voltage VDD and the NMOS transistor MN2 and the common node of the PMOS transistor MP2 and the ANMOS transistor MN2 are connected. It consists of inverters I2 and I3 for buffering and outputting.

In addition, the clock enable buffer 10 also has the same configuration as the circuit shown in FIG. 2, where the clock enable signal CKE is input to the input signal IN.

3 is a circuit diagram illustrating an input buffer enable signal generator shown in FIG. 1.

Referring to FIG. 3, the input buffer enable signal generation unit 30 receives the inverters I4 and I5 that receive and buffer the power-up signal pwrup, and the output signals of the inverter I5 as gates. The NMOS transistor MN5 having one side connected to the ground power supply VSS and the first clock enable signal cke2 output from the latch unit 20 are input to the gate, and one side thereof is connected to the other side of the NMOS transistor MN5. An inverter I6 that inverts the connected PMOS transistor MP4, the second clock enable signal cke2z, and outputs the output of the inverter I6 to a gate, and receives a power supply voltage VDD and a PMOS transistor. A PMOS transistor MP5 connecting the other side of the MP4 and an input of the output of the inverter I5 to the gate, and a PMOS transistor connecting the common node of the power supply voltage VDD and the PMOS transistors MP4 and MP5. To latch the signal applied to the common node of the MP6 and the PMOS transistors MP4 and MP5 Two inverters (I8, I7) and inverter chains (I9 ~ I11) for buffering and outputting the output of the inverter (I8) is provided.

Hereinafter, the operation of the clock enable buffer 1000 will be described with reference to FIGS. 1 to 3.

When power is initially applied to the semiconductor device, other external signals are also applied, which requires time for each input signal to stabilize. This is called a power-up mode. When the power-up mode ends, that is, when the power starts to be stably supplied, a power-up signal pwrup is generated.

On the other hand, the clock enable buffer 10 compares the clock enable signal CKE input from the outside with the reference signal Vref to the latch unit 20, and the latch unit 20 transmits the latched clock enable signal. Outputs (cke2, cke2z) to the input buffer enable signal generator 30.

When the power-up signal pwrup is enabled (logic level high), the first and second clock enable signals cke2 and cke2z output from the latch unit 20 are input buffer enable signal generator 30. ), The logic level low is applied to the input terminal of the inverter I8 constituting the latch, thereby enabling the input buffer enable signal BE to be low and output to the input buffers 11 to 16.

Subsequently, the input buffers 11 to 16 are enabled by the enabled input buffer enable signal BE to enable the external reference signal Vref and various control signals CS, RAS, CAS, and WE. Or) and the address signals A1, A0, .. are compared, and the result of the comparison is output to the latch sections 21 to 26. The signals latched in the latch units 21 to 26 are output to the semiconductor device and used to perform a series of operations.

However, as described above, since the clock enable buffer 10 of the semiconductor device is configured to receive an input by comparing an external reference signal Vref with a control signal, the power supply voltage VDD is applied to the clock enable buffer 10. In this first stabilized state, the reference signal Vref, the clock enable signal CKE, various control signals CS, RAS, CAS, WE ... or address signals A1, A0, .. are not properly stabilized. If not, it may be applied to the input buffers 11 to 16 and the clock enable buffer 10.

That is, the clock enable buffer 10 compares two input signals Vref and CKE when only the operating power supply voltage VDD is properly input, and starts transmitting the result to the latch unit 20.

Therefore, when the clock enable signal CKE is input with a large voltage level compared to the reference signal Vref while the two signals Vref and CKE are not stabilized, the clock enable signal CKE is input to the latch unit 20. Is passed.

The latch unit 20 outputs the first and second clock enable signals cke2 and cke2z by latching the transferred clock enable signal CKE. As a result, the input buffer enable signal generator 30 An input buffer enable signal BE for outputting all the input buffers 11 to 16 is output to the input buffer.

In this case, the plurality of input buffers 11 to 16 are in an enabled state, and various control signals CS, RAS, CAS, WE ... or address signals A1, A0, ... are not yet stabilized. In the state, it may be transferred into the semiconductor device through the input buffers 11 to 16 and the latch parts 21 to 26, which may cause an error in the initial operation of the semiconductor device.

The present invention provides a semiconductor device that controls an input buffer such that an external signal is transferred into a semiconductor after all input signals are stabilized in an initial operation mode in which power is first applied to the semiconductor device.

According to an aspect of the present invention, a plurality of normal input buffers each buffering a plurality of external signals are transferred to a inside of a semiconductor device; A clock enable buffer for receiving a clock enable command compared to a reference signal and outputting the clock enable command as a clock enable signal; A power-up mode input buffer that is enabled by a power-up signal, outputs an initial stabilization signal in response to an enable time of the clock enable command, and is disabled in response to a feedback of the initial stabilization signal; And an input buffer enable signal generator configured to enable the initial stabilization signal to generate an input buffer enable signal that receives the clock enable signal and enables the plurality of normal input buffers. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram showing a semiconductor device according to a preferred embodiment of the present invention.

Referring to FIG. 4, the semiconductor device according to the present embodiment buffers a plurality of external signals CS, RAS, CAS, WE ..., A1, A0, .., respectively, and delivers them to the inside of the semiconductor device. The clock enable buffer 100 for receiving the normal input buffers 110 to 160 and the clock enable command CKE from the reference signal Vref, and outputting them as clock enable signals cke2 and cke2z. After the power-up signal pwrup is enabled, an initial stabilization signal st is output in response to an enable time of the clock enable command CKE, and is disabled in response to a feedback of the initial stabilization signal st. The input buffer 400 for the power-up mode and the initial stabilization signal st are enabled, and receive the clock enable signals cke2 and cke2z to enable a plurality of normal input buffers 110 to 160. An input buffer enable signal generator 300 for generating the enable signal BE is provided.

In addition, the semiconductor device according to the present embodiment latches an output signal of the clock enable buffer 100 and outputs a latch unit 200 for outputting clock enable signals cke2 and ckez to the input buffer enable signal generator. It is further provided.

FIG. 5 is a circuit diagram illustrating an input buffer for the power-up mode shown in FIG. 4.

Referring to FIG. 5, the power-up mode input buffer 400 buffers and outputs an output of a first NAND gate ND2 and a first NAND gate ND2 that receive a power-up signal pwrup to one side. The first buffer unit I14 to I17, the second buffer unit I18 and I19 for buffering the output of the first NAND gate ND2 and outputting the initial stabilization signal st, and the first buffer unit An AND gate that receives the outputs of the outputs I14 to I17 on one side and receives the clock enable command CKE on the other side, and outputs the outputs to the other side of the first NAND gate ND2, wherein the NAND gate ND1 and the inverter ( I12).

In addition, the power-up mode input buffer 400 receives the power-up signal pwrup and the outputs of the first NAND gate ND1 on one side, and the second and third NANDs whose outputs are cross-coupled to each other. And an inverter I13 for inverting the outputs of the gates ND3 and ND4 and the third NAND gate ND4 and outputting them to the first buffer portions I14 to I17 and the second buffer portions I18 to I19. do.

FIG. 6 is a circuit diagram illustrating an input buffer enable signal generator shown in FIG. 4.

Referring to FIG. 6, the input buffer enable signal generator 300 includes a logic combination unit 310 for receiving and logically multiplying a power-up signal pwrup and an initial stabilization signal st, and one side of the ground power supply ( A first NMOS transistor MN6 and a clock enable signal cke2 that are connected to a VSS and connected to a gate of an output of the logic combination unit 310, and a clock enable signal cke2. The second PMOS transistor MN7 connected to the other side and the inverted clock enable signal cke2z are input to the gate, and the first PMOS connected to the other side of the power voltage VDD and the second NMOS transistor MN7. An output unit 320 for latching a signal applied to the common node of the transistor MP7 and the common node of the first PMOS transistor MP7 and the second NMOS transistor MP8 and outputting the signal as an input buffer enable signal BE. It is provided.

The logic combination unit 310 receives an initial stabilization signal st and inverts the inverter I23, a power-up signal ppwrup and the inverter I23. The NAND gate ND5 receives an output of the NAND gate. It is composed of an inverter (I24) for receiving the inverted output.

The output unit 320 of the input buffer enable signal generator includes a first inverter I18 that receives a common node of the first PMOS transistor MP7 and the second NMOS transistor MN7, and the first inverter I18. The second inverter I19 having an output connected to the input terminal of the first inverter I18 and the buffers I20, I21, and I22 for buffering and outputting the output of the first inverter I18. Equipped. In addition, the second PMOS transistor MP8 for supporting maintains the common node of the first PMOS transistor MP7 and the second NMOS transistor MP8 at a high level when the output of the inverter I24 is at a low level. It is to.

The clock enable buffer 100 has the same structure as the normal input buffer shown in FIG. 2 and receives a clock enable command CKE as an input signal IN.

FIG. 7 is a waveform diagram illustrating the operation of the semiconductor device illustrated in FIG. 4.

Hereinafter, the semiconductor device described above will be described with reference to FIGS. 4 to 7.

First, when power is supplied, the output of the NAND gate ND3 of the input buffer 400 for the power-up mode is high level because the power-up signal pwrup, which is still disabled, remains at the low level. The output of the gate ND4 maintains a low level.

After that, when the power starts to be stably supplied, a power-up signal pwrup indicating this is generated. The power-up signal pwrup generated at the high level is input to one side of the NAND gates ND3 and ND2 of the input buffer 400 for the power-up mode.

At this time, since the clock enable command CKE is still at the low level, the output of the inverter 12 is at the low level. Therefore, the output of the NAND gate ND4 is also at the low level. The initial stabilization signal st output through I19) is maintained at a high level.

Subsequently, when the clock enable command CKE is input to the NAND gate ND1 at a high level, the output of the inverter I12 is at a high level so that the output of the NAND gate ND4 is at a high level. Therefore, the initial stabilization signal st output through the inverter I19 is enabled at a low level.

On the other hand, the output of the inverter I17 is input low to the NAND gate ND1, and from this time, even if the clock enable command CKE is enabled and input, it cannot pass through the NAND gate ND1.

On the other hand, the clock enable buffer 100 transmits the clock enable command CKE to the latch unit 200 in comparison with the reference signal Vref, and the latch unit 200 receives the clock enable signals cke2 and cke2z. ) To latch and output.

Subsequently, the input buffer enable signal generator 300 receives the low level initial stabilization signal st and the high level power up signal pwrup to turn on the MOS transistor MN6. Subsequently, when the clock enable signals cke2 and cke2z are passed through the latch unit 200, the PMOS transistor MP7 is turned off, and the NMOS transistor MN7 is turned on to output a low level to the inverter I18. do. The above signals are latched by the two inverters I18 and I19, are enabled at a low level through the inverter I22, and output an input buffer enable signal.

FIG. 7 shows that the power-up signal pwrup is enabled at the high level and the initial stabilization mode st is enabled at the low level by the clock enable command CKE.

In the input buffer 400 for the initial stabilization mode of the semiconductor device according to the present invention described above, after the power supply voltage is initially applied, the clock enable command CKE is not compared with the reference signal Vref to receive the power-up. Generates an initial stabilization signal st when enabled at a sufficiently high level after the mode is applied.

When the initial stabilization signal st is input to the input buffer enable signal generator 300, the clock enable signal cke2 latched in the latch unit is output as the input buffer enable signal BE. Therefore, even though the clock enable buffer 100 initially transmits an unstable clock enable command after the power voltage is initially applied, compared to the reference signal Vref, the normal input buffer due to the initial stability and the mode st. The case where (11-16) is enabled does not occur.

Therefore, the semiconductor device according to the present invention can eliminate the unstable operation of the initial operation mode to which the power supply voltage is applied.

In addition, the input buffer for the power-up mode according to the present invention has a structure in which the power-up signal (pwrup) is enabled for the first time, the clock enable instruction is operated only once when it is first input, and is disabled by the initial stabilization signal. There is no current consumption.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, it is possible to prevent the unstable operation generated during the initial operation, which is the first power supply to the semiconductor device.

1 is a block diagram showing a semiconductor device according to the prior art;

FIG. 2 is a circuit diagram showing one of the input buffers shown in FIG.

3 is a circuit diagram illustrating an input buffer enable signal generator shown in FIG. 1; FIG.

4 is a block diagram showing a semiconductor device according to a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram showing an input buffer for the power-up mode shown in FIG.

FIG. 6 is a circuit diagram illustrating an input buffer enable signal generator shown in FIG. 4; FIG.

FIG. 7 is a waveform diagram showing the operation of the semiconductor device shown in FIG. 4; FIG.

Claims (6)

A plurality of normal input buffers each buffering a plurality of external signals and transferring the signals to the inside of the semiconductor device; A clock enable buffer for receiving a clock enable command compared to a reference signal and outputting the clock enable command as a clock enable signal; A power-up mode input buffer that is enabled by a power-up signal, outputs an initial stabilization signal in response to an enable time of the clock enable command, and is disabled in response to a feedback of the initial stabilization signal; And An input buffer enable signal generator configured to enable the initial stabilization signal to generate an input buffer enable signal that receives the clock enable signal and enables the plurality of normal input buffers; A semiconductor device comprising a. The method of claim 1, And latching means disposed between the clock enable buffer and the input buffer enable signal generator for latching the clock enable signal and outputting the clock enable signal to the input buffer enable signal generator. . delete The method of claim 1, The input buffer for the power-up mode A first NAND gate receiving the power up signal to one side; Second and third NAND gates each of which receives the power-up signal and the outputs of the first NAND gates on one side thereof, and whose outputs are cross-coupled to each other; An inverter for inverting and outputting an output of the third NAND gate; First buffering means for buffering the output of the inverter to output the initial stabilization signal; Second buffering means for buffering and outputting the output of the inverter; And And an AND gate configured to receive the output of the second buffering means to one side and to receive the clock enable command on the other side, and to output the output signal to the other side of the first NAND gate. The method of claim 1, The input buffer enable signal generator Logic combining means for receiving and multiplying the power-up signal and the initial stabilization signal; A first NMOS transistor having one side connected to a ground power source and having a gate connected to an output of the logic combining means; A second NMOS transistor receiving the clock enable signal as a gate and connected to the other side of the first NMOS transistor; A first PMOS transistor receiving the inverted clock enable signal as a gate and connected to a power supply voltage and the other side of the second NMOS transistor; And And an output unit configured to latch a signal applied to a common node of the first PMOS transistor and the second NMOS transistor to output the input buffer enable signal. The method of claim 5 The output portion of the input buffer enable signal generator A first inverter receiving a common node of the first PMOS transistor and the second NMOS transistor; A second inverter having an output terminal connected to an input terminal of the first inverter and an input terminal connected to an output terminal of the first inverter; And And a buffer for buffering and outputting the output terminal of the first inverter.