KR100219492B1 - Partial block repair means of memory cell and repair method using the same - Google Patents

Abstract

A partial block remedy for a memory cell and a partial block remedy using the same are disclosed. The partial block rescue means of the memory cell according to the present invention comprises an address input buffer for receiving an externally inputted external address in response to a predetermined control signal and outputting it as an internal address, Up control means for pulling up said internal address in response to an inverted signal of a pull-down control signal and pull-down means for pulling down said internal address in response to a predetermined input signal and a state of said first and second fuses, And control means for generating a pull-down control signal. Therefore, in a semiconductor memory device having a partial block remedy for a memory cell according to the present invention, when a defect occurs intensively in a specific partial block of a memory cell, a specific partial block in which a defect is caused by the partial block remedy There is an advantage in that the chip can be remedied by preventing access and allowing access only to the normal part.

Description

Partial block remedy for memory cells and partial block remedy using them

[0001] The present invention relates to a defect remedy for a memory cell in a semiconductor memory device and a fault remedy method using the same, and more particularly to a remedy for a partial block in which defects are intensively generated in memory cells and a remedy method using the same .

As the degree of integration of a semiconductor memory device, especially a DRAM, increases, the size of the memory cell (Cell) decreases, while the storage capacitor constituting the memory cell becomes more complicated in its fabrication process have. As a result, the failure rate exceeds the redundancy capacity as the failure rate of the memory cell increases, thereby increasing the number of chips that can not be relieved. In addition, when defects are generated intensively in a specific partial block of a memory cell, there is a problem that the chip can not be used even though the remaining memory cells except the specific partial block operate normally. Therefore, there is a need for a method capable of relieving a specific partial block in which defects are intensively generated as described above. For example, if only a portion of a memory cell that normally operates except for a specific partial block in which a defect occurs intensively can be accessed and used, only a part of the memory cells that are normally operated among the entire memory cell capacity is used, This is an effective remedy for chips generated intensively in this particular partial block. However, in the conventional semiconductor memory device, when a specific partial block is defective and the address is inputted from the outside, the specific partial block is also accessed, and therefore, it can not be used, and will be described in detail with reference to FIG. 1 and FIG.

1 shows a circuit diagram of a conventional address input buffer in a semiconductor memory device.

Referring to FIG. 1, the conventional address input buffer includes a first inverting means 1 for inverting an external address YAD11 input from the outside in response to an address control signal ACONT1, Down means (N2) for pulling down the output port of the first inverting means (1) in response to the first inverting means (1); a second inverting means (I1) for inverting the output signal of the first inverting means (TM) for transferring an output signal of the second inverting means (I1) in response to an address control signal (ACONT2), and a latch circuit for latching a signal transferred through the switching means (TM) And latch means 3 for outputting the inverted data YA11B thereof. The first inverting means 1 is configured such that two PMOS transistors P1 and P2 and one NMOS transistor N1 are connected in series between a power supply voltage VCC and a ground voltage VSS have. The pull-down means N2 is comprised of an NMOS transistor, and the receiving means TM comprises a transmission gate. The second inverting means I1 is constituted by an inverter and the latch means 3 is constituted by inverters I4, I5 and I6.

Hereinafter, the operation will be described with reference to FIG. When the address control signal ACONT1 becomes logic low, the output value of the second inverting means I1 is determined in accordance with the level of the external address YAD11 input from the outside, and in response to another address control signal ACONT2, The output value of the second inverting means I1 is output as the internal address YA11 and its inverted data YA11B. That is, when the address control signal ACONT1 is logic low and the external address YAD11 is logic high, the output of the second inverting means I1 becomes logic high, and at this time, the other address control signal ACONT2 becomes logic high The output value of the second inverting means I1 is stored in the latch means 3 via the switching means TM. Therefore, a logic high is outputted to the internal address YA11 which is the output of the latch means 3, and a logic low is outputted to the inverted data YA11B thereof. As described above, in the conventional address input buffer, the internal address YA11 is determined according to the level of the external address YAD11 input from outside, thereby accessing the partial block of the memory cell.

FIG. 2 is a diagram showing a case where defects are intensively generated in a specific partial block of a memory cell in a semiconductor memory device. FIG. YA11 and YA11B represent the internal address and its inversion data determined by the 11th bit YAD11 of the external Y address input from the outside and XA11 and XA11B represent the internal address and inverted data thereof determined by the 11th bit XAD11 of the externally input X address Address and its inverted data. Here, it is shown that a failure occurs in a partial block in which the internal address YA11 and its inverted data YA11B, which are selected by inputting the external address YAD11 at a logic low, are logic low and logic high, respectively.

However, in the semiconductor memory device having the conventional address input buffer as described above, when a failure is intensively generated in a specific partial block of a memory cell as shown in FIG. 2, if an external address is input from the outside, The memory is accessed, so that even though the memory cells other than the specific partial block operate normally, the chip can not be used.

It is therefore an object of the present invention to provide a memory cell capable of rescuing a chip by preventing a specific partial block in which a defect is generated from being accessed and accessing only a normal region in a case where a defect occurs intensively in a specific partial block of the memory cell And to provide a partial block remedy.

Still another object of the present invention is to provide a partial block remedy method of a memory cell using the partial block remedy.

1 is a circuit diagram of a conventional address input buffer in a semiconductor memory device.

2 is a view showing a case where a defective part is concentrated on a specific partial block of a memory cell in a semiconductor memory device

3 is a circuit diagram of a partial block remedy for a memory cell according to an embodiment of the present invention.

According to an aspect of the present invention, there is provided a partial block remedy for a memory cell, comprising: an address input buffer for receiving an external address input from the outside in response to a predetermined control signal and outputting the address to an internal address; Up means for pulling up the internal address which is an output of the address input buffer; pull-down means for pulling down the internal address in response to an inverted signal of the pull-down control signal; And a control means for generating the pull-up control signal and the pull-down control signal in response to the control signal.

According to a preferred embodiment, the address input buffer includes: first inverting means for inverting the external address in response to a first control signal among the predetermined control signals; and first inversion means for inverting the external address in response to the predetermined first control signal, A second inverting means for inverting an output signal of the first inverting means and a second inverting means for inverting an output signal of the second inverting means in response to a second control signal of the predetermined control signal, And latch means for latching the signal transferred through the switching means and outputting the internal address. The control means includes a pulse generating means for generating a pulse in response to the predetermined input signal, and a second fuse including the first fuse and outputting the first data as the pull-up control signal when the first fuse is not cut off Up control signal in response to an output pulse of the pulse generating means in a state in which the first fuse is cut off; and a first latch means including the second fuse and the second fuse is cut A second latch means for outputting the first data as the pull-down control signal in a state where the first data is not output and the second data as the pull-down control signal in response to the output pulse of the pulse generating means when the second fuse is cut off . The first data is a logic high and the second data is a logic low.

According to another aspect of the present invention, there is provided a partial block remedy method for a memory cell, comprising: an address input buffer receiving an external address input from the outside in response to a predetermined control signal and outputting the address to an internal address; Up means for pulling up the internal address which is the output of the address input buffer in response to an inverted signal of the pull-down control signal, pull-down means for pulling down the internal address in response to an inverted signal of the pull- And a control means for generating the pull-up control signal and the pull-down control signal in response to a state of the first and second fuses, wherein the semiconductor memory device cuts off a selected one of the first and second fuses, Up and pull-down control signals, and the pull-up and pull-down control And an input blocking signal of the address input buffer is generated by any one of the pull-up and pull-down control signals to prevent the external address from being inputted. And activates one of the address input buffers to fix the internal address, which is an output of the address input buffer, to any one of a logic high and a logic low.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a circuit diagram of a partial block remedy for a memory cell according to an embodiment of the present invention. Here, the same reference numerals and the same reference numerals are used for the same elements as those of the conventional address input buffer of FIG.

3, the partial block remedy means of the memory cell receives an external address YAD11 inputted from outside in response to predetermined address control signals ACONT1 and ACONT2 and a control signal FCONT, The address input buffer 10 for outputting the inverted data YA11 and YA11B in response to the pull-up control signal ENAH and the internal address YA11 being the output of the address input buffer 10 in response to the pull- Down means 30 for pulling down the internal address YA11 in response to an inverted signal of the pull-down control signal ENAL, that is, a logic low, Up control signal ENAH and a pull-down control signal ENAL in response to a state of the first and second fuses F1 and F2.

The address input buffer 10 is controlled by the output of the NOR gate NR1 to which the switching means TM receives the address control signal ACONT2 and the control signal FCONT output from the control means 40 1, and the other components are the same as the conventional address input buffer of FIG. The pull-up means 20 is constituted by a PMOS transistor P3, and the pull-down means 30 is constituted by an NMOS transistor N3. The control means 40 further includes a pulse generating means 40a for generating a positive pulse in response to the predetermined input signal PMASTER and a second fuse F1 including the first fuse F1, Up control signal (ENAH) in response to an output pulse of the pulse generating means (40a) when the first fuse (F1) is disconnected, A first latch means 40b for outputting the second data of the logic high level to the pull-up control signal ENAH and a second latch means 40b for outputting the second data of the logic high level when the second fuse F2 is disconnected Down control signal ENAL while the second data of the logic low is outputted in response to the output pulse of the pulse generating means 40a in the state that the second fuse F2 is disconnected, And second latch means 40c for outputting an output signal ENAL.

The pulse generating means 40a of the control means 40 includes a delay means composed of an odd number of inverters I7, I8 and I9 for inverting and delaying the predetermined input signal PMASTER, (PMASTER) and a NOR gate (NR2) for performing an AND operation on the outputs of the delay means and inverting the outputs. The first and second latch means 40b and 40c have the same configuration and include first and second fuses F1 and F2, one end of which is connected to the power supply voltage VCC, The NMOS transistors N4 and N6 whose drains are connected to the other ends of the fuses F1 and F2 and whose sources are connected to the ground voltage VSS and whose gates are connected to the output terminals of the pulse generating means 40a, And inverting means I10 and I12 for inverting a value outputted from a connection point between the first and second fuses F1 and F2 and the NMOS transistors N4 and N6; Another NMOS transistor N5 and N7 whose drain is connected to the other end and whose source is connected to the ground voltage VSS and whose gate is connected to the output terminal of the inverting means I10 and I12 and the inverting means I10 and I12 (I11, I13) for inverting the output of the pull-down control signal ENAH and the pull-down control signal ENAL, respectively.

Hereinafter, the operation of the partial block remedy means of the memory cell and the partial block remedy method according to the embodiment of the present invention will be described with reference to FIG. First, when the semiconductor memory device is initialized, the predetermined input signal PMASTER toggles from a logic high to a logic low. The predetermined input signal PMASTER is delayed in a delay means composed of inverters I7, I8 and I9, and a positive pulse is generated in the pulse generating means 40a. When the first and second fuses F1 and F2 are not disconnected, the pull-up control signal ENAH, which is an output of the first latch means 40b, maintains a logical high, The pull-down control signal ENAL, which is the output of the NAND gate 40c, also maintains a logical high, and the control signal FCONT, which is the output of the NAND gate ND serving as an input thereof, becomes logic low. As a result, the PMOS transistor P3 as the pull-up means 20 is turned off and the pull-down control signal ENAL of the logic high is inverted by the inverter I14 so that the NMOS transistor N3 Is also turned off. In this case, it operates in the same manner as the conventional address input buffer of FIG.

Next, as shown in FIG. 2, when the internal address YA11 and its inverted data YA11B, which are selected by inputting the external address YAD11 at a logic low, are defective in the partial block having logic low and logic high, respectively , It is possible to remedy the defective partial block by fixing the internal address YA11 to logic high irrespective of the external address YAD11. That is, when the first fuse F1 is disconnected, the PMOS transistors N4 and N5 are turned on by the positive pulse generated by the pulse generating means 40a so that the pull-up control signal ENAH becomes logic low, The signal FCONT becomes logic high. As a result, the output of the NOR gate NR1, which receives the control signal FCONT of the logic high, in the address input buffer 10 becomes a logical low and the transmission gate which is the switching means TM is turned off, Block input. The PMOS transistor P3 which is the pull-up means 20 is activated or turned on by the pull-up control signal ENAH enabled by the logic low so that the data of the logic high is latched by the latch means of the address input buffer 10 3, and fixes the internal address YA11 and its inverse data YA11B, which are the outputs of the address input buffer 10, to logic high and logic low, respectively. Therefore, regardless of the external address YAD11 input from the outside, the partial block in which a failure occurs is not accessed, and only the partial block in which no failure occurs, that is, the partial block in which the internal address YA11 is logic high, is always accessed. 2, when a failure occurs in a partial block in which the internal address YA11 and its inverted data YA11B, which are selected by inputting the external address YAD11 at a logical high, are logic high and logic low, respectively, By fixing the inverted data YA11B of the internal address YA11 to logic high irrespective of the address YAD11, the defective partial block can be rescued. That is, when the second fuse F2 is cut, the internal address YA11 and its inverse data YA11B, which are the outputs of the address input buffer 10, are fixed to logic low and logic high, respectively. This operation is the same as the operation in the case where the first fuse F1 is disconnected, and a detailed description thereof will be omitted.

Therefore, in a semiconductor memory device having a partial block remedy for a memory cell according to the present invention, when a defect occurs intensively in a specific partial block of a memory cell, a specific partial block in which a defect is caused by the partial block remedy There is an advantage in that the chip can be remedied by preventing access and allowing access only to the normal part.

Claims (13)

An address input buffer receiving an external address input from the outside in response to a predetermined control signal and outputting the external address as an internal address; Up means for pulling up the internal address which is an output of the address input buffer in response to a pull-up control signal; Pull down means for pulling down said internal address in response to an inverted signal of a pull down control signal; And control means for generating the pull-up control signal and the pull-down control signal in response to a predetermined input signal and a state of the first and second fuses. 2. The semiconductor memory device according to claim 1, wherein the address input buffer comprises: first inverting means for inverting the external address in response to a first control signal of the predetermined control signal; A second inverting means for inverting an output signal of the first inverting means and a second inverting means for inverting an output signal of the second inverting means in response to a second control signal of the predetermined control signal, And latch means for latching the signal transferred through said switching means and outputting said internal address. 2. The apparatus according to claim 1, wherein the control means comprises: pulse generating means for generating a pulse in response to the predetermined input signal; Up control signal and outputting the second data as the pull-up control signal in response to an output pulse of the pulse generating means when the first fuse is disconnected; and a second latch circuit including the second fuse, And outputs the first data as the pull-down control signal when the second fuse is not cut off, and outputs the second data as the pull-down control signal in response to the output pulse of the pulse generating means when the second fuse is cut off And a second latch means. 4. The means of claim 3, wherein the first data is a logic high and the second data is a logic low. 4. The semiconductor memory device according to claim 3, wherein the first latch means comprises: a first fuse whose one end is connected to a power supply voltage; and a second fuse whose drain is connected to the other end of the first fuse, An inverting means for inverting a value output from a connection point between the first fuse and the NMOS transistor; a drain connected to the other end of the first fuse and a source connected to a ground voltage; Further comprising another NMOS transistor having a gate connected to an output terminal of the inverting means and another inverting means for inverting the output of the inverting means and outputting the inverted output as the pull-up control signal. 4. The semiconductor memory device according to claim 3, wherein the second latch means comprises: a second fuse whose one end is connected to a power supply voltage; a second fuse having a drain connected to the other end of the second fuse and having a source connected to a ground voltage, An inverting means for inverting a value output from a connection point between the second fuse and the NMOS transistor; a drain connected to the other end of the second fuse and having a source connected to a ground voltage; And another inverting means for inverting an output of the inverting means and outputting the inverted output of the inverting means with the pull-down control signal. Up means for pulling up the internal address which is an output of the address input buffer in response to a pull-up control signal, pull-down control means for pulling up the pull- Down means for pulling down the internal address in response to an inverted signal of the signal and control means for generating the pull-up control signal and the pull-down control signal in response to a predetermined input signal and a state of the first and second fuses. In the memory device, Cutting any one of the first and second fuses and inputting the predetermined input signal to enable any one of the pull-up and pull-down control signals; Generating an input blocking signal of the address input buffer by any one of the pull-up and pull-down control signals to block input of the external address; And activating any one of the pull-up and pull-down means by any one of the pull-up and pull-down control signals to fix the internal address as an output of the address input buffer to any one of a logic high and a logic low. Of the memory cells. And an address input buffer for receiving an externally input external address in response to a predetermined control signal and outputting the external address as an internal address, wherein the internal address is fixed to a predetermined value irrespective of the external address, And a partial block remover of the memory cell for accessing a specific part of the memory cell. 9. The semiconductor memory device according to claim 8, wherein the partial block remedy means of the memory cell comprises: pull-up means for pulling up the internal address which is an output of the address input buffer in response to a pull-up control signal; And control means for generating the pull-up control signal and the pull-down control signal in response to a predetermined input signal and a state of the first and second fuses. 10. The image pickup apparatus according to claim 9, wherein the control means comprises: pulse generating means for generating a pulse in response to the predetermined input signal; Up control signal and outputting the second data as the pull-up control signal in response to an output pulse of the pulse generating means when the first fuse is disconnected; and a second latch circuit including the second fuse, And outputs the first data as the pull-down control signal when the second fuse is not cut off, and outputs the second data as the pull-down control signal in response to the output pulse of the pulse generating means when the second fuse is cut off And a second latch means. 11. The semiconductor memory device of claim 10, wherein the first data is a logic high and the second data is a logic low. 11. The semiconductor memory device according to claim 10, wherein the first latch means comprises: a first fuse whose one end is connected to a power supply voltage; a second fuse having a drain connected to the other end of the first fuse, An inverting means for inverting a value output from a connection point between the first fuse and the NMOS transistor; a drain connected to the other end of the first fuse and a source connected to a ground voltage; Further comprising another NMOS transistor having a gate connected to the output terminal of the inverting means and another inverting means for inverting an output of the inverting means and outputting the pull-up control signal. 11. The semiconductor memory device according to claim 10, wherein the second latch means comprises: a second fuse whose one end is connected to a power supply voltage; a second fuse having a drain connected to the other end of the second fuse and having a source connected to a ground voltage, An inverting means for inverting a value output from a connection point between the second fuse and the NMOS transistor; a drain connected to the other end of the second fuse and having a source connected to a ground voltage; And another inverting means for inverting an output of the inverting means and outputting the inverted output of the inverting means with the pull-down control signal.