KR100869217B1 - display data bit check circuit for FPD driver - Google Patents

Abstract

The present invention relates to a display data bit check circuit for a flat panel display device driver capable of reducing chip size and reducing power consumption. An efficient display data bit check circuit of the present invention includes: test signal generating means for generating a test signal of a power supply voltage or a ground level in a test line according to a test pattern; And a check means for checking the test signal and data bits generated in the test line from the test signal generating means according to the test enable signal. The efficient display data bit check circuit of the present invention consists of only one transistor for each data bit and checks the data bit, thereby reducing the circuit area and operating only in the test mode, thereby reducing power consumption.

Chip Size, Power Consumption, Flat Panel Display, Driver, Display, Data Bits

Description

Display data bit check circuit for FPD driver

1 is a two-sided view for explaining a data access method of a conventional TFT-LCD driver,

2 is a block diagram of a conventional display data bit check circuit for a flat panel display device driver;

3 is a block diagram of an efficient display data bit check circuit of a flat panel display device driver according to an exemplary embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

100: test signal generating means 200: check means

300, 310: test lines 112, 121: PMOS transistors

111, 122, 210, 212, 221, 223: NMOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display driver, and more particularly, to an efficient display data bit check circuit that can reduce power consumption by reducing circuit area for a TFT-LCD driver.

Drivers of flat panel display devices such as TFT-LCD (Thin Film Transistor-Liquid Crystal Display) are largely composed of controller, source driver, gate driver, and power IC. Recently, drivers of flat panel display devices have been integrated with controllers and source drivers in accordance with the demand for technological advancement and low price. The integration of the controller and the source driver is accelerated due to the advantages of power consumption, circuit area, and price by performing the interface inside the IC due to the characteristics of the display driver requiring a large amount of data transmission.

1 is a view for explaining a method of accessing data from a memory in a TFT-LCD driver in which a controller and a source driver are integrated.

As illustrated in FIG. 1, in a TFT-LCD driver in which a controller and a source driver are integrated, data is read from and written to the memory 11 in units of bytes or words in a MCU, and is independently displayed. For parallel transmission, the source driver circuit 12 integrates a large amount of data in line units.

Conventionally, a circuit for checking the display data bits as shown in FIG. 2 has been used to verify the data path from the memory 11 to the source driver circuit 12.

2 is a block diagram of a conventional display data bit check circuit for a flat panel display device driver.

Referring to FIG. 2, the conventional display data bit check circuit includes the even-numbered data bits (bit0, bit2, ...) and the even-bit test pattern (of the plurality of data bits (bit0, bit1, bit2, bit3, ...). A number of exclusive oragates (XOR0, XOR2, ...), radix data bits (bit1, bit3, ...) and radix bits for checking even data bits by entering even bit test pattern (EBTP) A plurality of exclusive OR gates (XOR1, XOR3, ...) for checking odd data bits by inputting an odd bit test pattern (OBTP), and the exclusive OR gates (XOR0, XOR2,. Ora gate for outputting a test result for even data bits by inputting an output signal of ..) and an output signal of the exclusive oragate (XOR1, XOR3, ...) It consists of an OR gate OR1 for outputting a test result for the bit.

The operation of the conventional display data bit check circuit having the configuration as described above is as follows.

The test driver writes a test pattern such as "010101 ..." or "101010 ..." into the memory 11 in the MCU (not shown in the drawing), and uses a source driver circuit using a control signal of the panel access stage. The display data bits are transmitted to (12).

At the same time, the exclusive ora gates XOR0, XOR2, ... check whether the even data bits bit0, bit2, ... coincide with the even bit test pattern EBTP from the memory 11 Output to the OR gate OR0, and the odd data bits (bit1, bit3, ...) through the exclusive ora gate (XOR1, XOR3, ...) from the memory 11 to the odd bit test pattern Check if it matches (OBTP) and provide to OR gate OR1.

Therefore, the IC is tested by checking the outputs of the OR gates OR0 and OR1. If there is an error in the even data bit or the odd data bit, the output of the OR gate OR0 or OR1 is " high state. (H) ", therefore, the output of the OR gates OR0 and OR1 is checked for abnormality.

The conventional display data bit check circuit as described above uses a checkered pattern in which adjacent upper, lower, left, and right cells of the memory test method write logic values opposite to the center cell. The short between bits was checked.

However, since the check circuit is allocated one exclusive oragate for each bit and requires an ora gate for integrating the output of each exclusive ora gate, a flat panel display device in which display data bits of thousands or more bits are transmitted. Due to the nature of the circuit area was significantly increased. In addition, since the operation of the exclusive orifice continues in the normal mode instead of the test mode, there is a problem in that unnecessary power consumption occurs. Therefore, there is a problem that is very difficult to apply to a flat panel display device for mobile devices.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide an efficient display data bit check circuit of a flat panel display device driver capable of reducing area and reducing power consumption.

The present invention for achieving the above object includes a test signal generating means for generating a test signal of the power supply voltage or ground level in the test line according to the test pattern; A display data bit check circuit of a flat panel display device driver comprising a check means for checking a test signal and a data bit generated in a test line from the test signal generating means according to a test enable signal.

The test signal generating means includes: first generating means for generating a good test signal on the good test line according to the test pattern; And second generating means for generating a radix test signal in the radix test line according to the test pattern.

The checking means includes means for checking the even data bits of the data bits with the good test signal applied to the good test line according to the test enable signal; And a means for checking an odd test signal to which odd data bits of the data bits are applied to the odd test line according to the test enable signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.                     

3 is a block diagram of an efficient display data bit check circuit of a flat panel display device driver according to an exemplary embodiment of the present invention.

Referring to FIG. 3, an efficient display data bit check circuit according to an exemplary embodiment of the present invention generates a test signal for generating a test signal of a power supply voltage VDD or ground GND level in a test line according to a test pattern TP. The test signal and the data bits (bit0, bit1, bit2, bit3, ...) generated in the test line from the test signal generating means 100 are checked according to the means 100 and the test enable signal TE. It is provided with a check means (200).

The test signal generating means 100 performs a nose test on the radix test line 310 according to the first generating means and the test pattern TP generating the good test signal on the good test line 300 according to the test pattern TP. And second generating means for generating a signal.

The first generating means of the test signal generating means 100 has a drain connected to a power supply voltage VDD and a ground GND, a test pattern TP provided to a gate, respectively, and an excellent test signal through a common connected source. The NMOS transistor 111 and the PMOS transistor 112 are generated. In the second generating means, the source is connected to the power supply voltage VDD and the ground GND, respectively, and the test pattern TP is provided to the gate, respectively. The PMOS transistor 121 and the NMOS transistor 122 generating the odd test signal through the connected drain.

The check means 200 is the even data bit (bit0, bit2, ...) and the good test line 300 of the data bits (bit0, bit1, bit2, bit3, ...) according to the test enable signal (TE) Means for checking the even test signal applied to the < RTI ID = 0.0 > 1) < / RTI > and the odd data bits (bit1, bit3, ...) of the data bits (bit0, bit1, bit2, bit3, ...) according to the test enable signal TE. And a radix test signal applied to the radix test line 310.

The even data bit checking means of the check means 200 includes a plurality of NMOS transistors for checking the even data bits bit0, bit2, ... with the good test signal according to the test enable signal TE applied to the gate. NMOS transistors 210, 212, ... are arranged corresponding to each even data bit (bit0, bit2, ...).

The odd data bit checking means of the check means 200 includes a plurality of NMOS transistors for checking the odd data bits bit 1, bit 3,... With the odd test signal according to a test enable signal TE applied to a gate. (221, 223, ...), one NMOS transistor (221, 223, ...) is arranged corresponding to each odd data bit (bit1, bit3, ...).

The operation of the efficient display data bit check circuit of the present invention having the configuration as described above is as follows.

First, since the test enable signal TE is disabled in the normal mode, the NMOS transistors 210, 212, ..., 221, 223, ... of the check means 200 are not driven. .

In the test mode, since the test enable signal TE is enabled, the check block 200 operates to check the display data bit with the test signal.

That is, the test signal generating means 100 generates the odd test signal and the even test signal to the odd test line 310 and the even test line 300 according to the test pattern TP. When the test pattern TP is at the low level (L), the test signal generating means 100 provides the excellent test signal of the ground (GND) level through the first means composed of the NMOS transistor 111 and the PMOS transistor 112. The test line 300 is generated, and at the same time, a radix test signal having a power supply voltage VDD level is generated in the radix test line 310 through a second means including the PMOS transistor 121 and the NMOS transistor 122.

On the contrary, if the test pattern TP is at the high level H, the test signal generating means 100 generates the good test signal of the power supply voltage VDD level to the good test line 300 through the first means. At the same time, a radix test signal having a ground (GND) level is generated to the radix test line 310 through the second means.

The check means 200 checks the data bit and the even test signal and the odd test signal generated from the test signal generating means 100. The NMOS transistors 210, 212, ... of the even data bit check means are driven by a test enable signal TE, and the even data bits (bot0, bit1, bit2, bit3, ...) of the data bits (bot0, bit1, bit3, ...) are driven. If bit0, bit2, ...) is the same level as the even test signal applied to the good test line 300, a current path is not formed and thus a large amount of current does not flow. However, when the even data bits (bit0, bi2, ..) and the even test signal are not at the same level, a DC current path is formed so that a large amount of current flows.                     

Similarly, the NMOS transistors 221, 223, ... of the odd data bit check means are driven by the test enable signal TE, and the odd number of the data bits bot0, bit1, bit2, bit3, ... If the data bits bit1, bit3, ... are at the same level as the odd test signal applied to the odd test line 310, a current path is not formed and thus a large amount of current does not flow. However, when the odd data bits (bit1, bi3, ...) and the odd test signal are not at the same level, a DC current path is formed, so a large amount of current flows.

Therefore, the current flows through the NMOS transistors 210, 212, ... for checking the even data bit of the check means 200 and the NMOS transistors 221, 223, ... for checking the odd data bit. The display data bit is checked.

In the present invention, the display data bits are separated into even data bits and odd data bits using a checkered pattern, and the test lines are connected in parallel to each other without performing a test for each display data bit. Check the data bits.

In the embodiment of the present invention, the check means 200 is composed of only NMOS transistors, but may be composed of PMOS transistors or PMOS transistors and NMOS transistors. In addition, when the test pattern is not a checkered pattern, the test signal generated by the test signal generating unit 100 may be provided in other forms instead of the even data bit or the odd data bit according to the test pattern.

According to the present invention as described above, by implementing the check means with only one transistor for each data bit, it is possible to check the display data bits efficiently with a simple circuit configuration, thereby reducing the circuit area. In addition, when the test mode is not in the test mode, power consumption can be reduced by preventing unnecessary operation of the check circuit.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (7)

Test signal generating means for generating a test signal of a power supply voltage or a ground level in a test line according to the test pattern; And Check means for checking a test signal and a data bit generated in the test line from the test signal generating means according to a test enable signal And a display data bit check circuit of the flat panel display device driver. The method of claim 1, The test signal generating means, First generating means for generating a good test signal to a good test line according to the test pattern; And Second generating means for generating a radix test signal to the radix test line according to the test pattern; And a display data bit check circuit of the flat panel display device driver. The method of claim 2, The first generating means includes display data of a flat panel display device driver including an NMOS transistor and a PMOS transistor, each having a drain connected to a power supply voltage and a ground, a test pattern provided at a gate, and generating a good test signal through a common connected source. Bit check circuit. The method of claim 2, The second generating means includes display data of a flat panel display device driver including a PMOS transistor and an NMOS transistor, each having a source connected to a power supply voltage and a ground, a test pattern provided to a gate, and generating an odd test signal through a common connected drain. Bit check circuit. The method of claim 1, The check means, Means for checking the even data bit of the data bits with the good test signal applied to the good test line according to the test enable signal; And Means for checking the odd data bits of the data bits with the odd test signal applied to the odd test line according to the test enable signal And a display data bit check circuit of the flat panel display device driver. The method of claim 5, wherein The good data bit check means of the check means includes a plurality of NMOS transistors for checking the good data bits with the good test signal according to the test enable signal applied to the gate, so that one NMOS transistor corresponds to each good data bit. The display data bit check circuit of the flat panel display device driver is arranged. The method of claim 5, wherein Among the check means, the odd data bit check means comprises a plurality of NMOS transistors for checking the odd data bits with the odd test signal according to the test enable signal applied to the gate, so that one NMOS transistor corresponds to each odd data bit. The display data bit check circuit of the flat panel display device driver is arranged.

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