JPH0313680B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory whose memory contents can be erased by ultraviolet irradiation or the like.

[Prior art]

In recent years, with the rapid development of microcomputers, a field called read-only memory (hereinafter referred to as ROM) has grown significantly. ). The ROM is
This memory has a relatively simple structure, high degree of integration, low cost, and has no write function or even if it has a write function, its performance may be lower than that of a random access memory.

The most basic type of ROM stores information in the mask pattern used in the IC manufacturing process, and is called a mask ROM. Although it is impossible to change the memory contents, the reliability of writing and the stability of storage are very good, and the unit price is low when making large quantities of the same memory contents, but it is not suitable for low-volume, high-mix products. It is not suitable for this purpose, and it takes a considerable amount of time from when the pattern information is obtained from the user until it becomes a product.
On the other hand, programmable ROM is a ROM that allows the user to freely write the memory contents using fields.
In the present invention, the non-volatile semiconductor memory (hereinafter referred to as
It's called EPROM. ) is one type of this. EPROM
ROM requires a special package for UV irradiation, and has the disadvantage of being more expensive than ROM. However, it has excellent usability in the field and has formed a large market.

By the way, the storage stability of EPROM, that is, the retention characteristics after information is written, is extremely good.
It is known that it can be used as a sufficient substitute for ROM. Therefore, instead of using a special package, we use a package similar to ROM, such as a plastic package, which eliminates the need to erase the memory contents and is limited to one-time writing, so that it can be used not only in small quantities of many types, but also in large quantities. EPROM (hereinafter referred to as "one-write EPROM") was considered because even if the unit price is extremely low, it is convenient in the field, and it can be obtained by users in a short period of time. However, in this case, the functionality of the product is checked only when the wafer is in its pre-assembly state, and after assembly, it is limited to checking only when no data is stored. Although the unit price is low, there is a high proportion of products that cause data writing defects to users. Furthermore, it is not possible to sufficiently check the normal data read time, so-called access time.

FIG. 1 is a block diagram showing the configuration of an example of a conventional EPROM. This conventional example has an 8-bit input/output configuration, and the input/output of information to the memory _cell matrix 6 is controlled by the input/output controller 1 by selecting the column decoder 2 and row decoder 3 using address inputs A _p to A n. Therefore, it is performed via the input/output buffer 4. In the figure, 5 is a column selector, C is a control signal,
_O0-7 are input/output data _signals .

In this configuration, a check function for checking the EPROM function is not added, so as mentioned above, the function check for the product can only be performed by checking with a probe on the wafer, and it may not be possible to perform a sufficient check after assembly. There is a drawback.

[Purpose of the invention]

An object of the present invention is to provide a high-yield, highly reliable nonvolatile semiconductor memory equipped with a test circuit by eliminating the above drawbacks.

[Structure of the invention]

The nonvolatile semiconductor memory of the present invention includes a plurality of memory cells arranged in row and column directions, and a memory cell matrix that writes normal data to a specified address and reads data from a specified address. , which has a plurality of dummy cells corresponding to the memory cells in the row direction of this memory cell matrix and is provided across the memory cell matrix, writes test data to a specified address when in a selected state, and writes test data to a specified address. a plurality of dummy cells corresponding to the memory cells in the column direction of the memory cell matrix; A plurality of column dummy cells are provided corresponding to each bit of data read from the test block, and write test data to a specified address when selected, and read data from a specified address. A row decoder that specifies the row address of the memory cell matrix and the group of column dummy cells with a first address input; and a column decoder that specifies the column address of the memory cell matrix and the group of row dummy cells with the second address input when activated. and a column selector, a dummy row decoder that selects one of the at least two row dummy cell groups when activated, and a dummy column decoder and a dummy column selector that select the column dummy cell group when activated. and,
When a specific bit of the first address input is at a predetermined level equal to or higher than the power supply voltage, the dummy row decoder is activated and the row decoder is inactivated, and when the particular bit is equal to or lower than the power supply voltage. a test row address buffer that deactivates the dummy row decoder and activates the row decoder when the voltage is at the normal logic level; When the voltage is at a predetermined level higher than the voltage, the dummy column decoder and dummy column selector are activated and the decoder and column selector are inactivated. A test column address buffer that deactivates the dummy column decoder and dummy column selector and activates the column decoder and column selector when the logic level is normal, the memory cell matrix, and the row dummy cell group. , and an input/output buffer for transmitting data for writing to a group of column dummy cells and outputting data read from the memory cell matrix, a group of row dummy cells, and a group of column dummy cells to the outside. .

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention. Note that this figure shows one bit of EPROM consisting of input/output Z bits.

This embodiment includes a memory cell matrix 16 that includes a plurality of memory cells arranged in row and column directions, writes normal data to a specified address, and reads data from a specified address, and It is provided with a plurality of dummy cells corresponding to the memory cells in the row direction of the cell matrix 16, and is provided with the memory cell matrix 16 in between, and writes test data to a specified address when in a selected state, and writes test data to a specified address. It is provided with two row dummy cell groups 23 and 24 for reading data from an address, and a plurality of dummy cells corresponding to the memory cells in the column direction of the memory cell matrix 16, and for reading data written to the memory cell matrix 16 and this memory cell matrix. A plurality of column dummy cell groups 25 are provided corresponding to each bit of read data from the test block, and write test data to a specified address when in a selected state, and read data from a specified address. When the first address is input
A row decoder 13 that specifies the row address of the memory cell matrix 16 and column dummy cell group 25 using A _o+1 to _{A n} , and a second address input when activated.
A column decoder 12 and a column selector 15 specify column addresses of the memory cell matrix 16 and row dummy cell groups 23 and 24 by _{A p} to _{A o} , and one of the two row dummy cell groups 23 and 24 when activated.
Dummy row decoders 20 and 21 with one selected state
, the dummy column decoder 19 and dummy column selector 22 which select the column dummy cell group 25 when activated, and a specific bit A _n of the first address inputs A _o+1 to _{A n} are set to a predetermined value higher than the power supply voltage. When the specific bit A _n is at the normal logic level below the power supply voltage, the dummy row decoders 20 and 21 are activated and the row decoder 13 is deactivated. A test row address buffer (BX) 18 that activates the row decoder 13 as well as a dummy column decoder 19 and a dummy column selector 22 when a specific bit A _o is at a predetermined level higher than the power supply voltage. is activated and the column decoder 12 and column selector 15 are inactivated, and when the specific bit A _o is at a normal logic level below the power supply voltage, the dummy column decoder 19 and dummy column selector 22 are activated.
to the test column address buffer (BY) 17, which deactivates the column decoder 12 and the column selector 15, and the memory cell matrix 16, the row dummy cell groups 23 and 24, and the column dummy cell group 25. An input/output buffer 1 transmits data for writing, and outputs data read from the memory cell matrix 16, row dummy cell groups 23 and 24, and column dummy cell group 25 to the outside.
4 and an input/output controller 11 that controls the operation of the input/output buffer 14.

In this example, the input/output of information to _/ from the memory cell matrix 16 is performed by the input/output controller 11 via the input/output buffer 14 by selection of the column decoder ₁₂ and row decoder 13 based on address inputs A p to A n. In the figure, 15 is a column selector, C is a control signal, and _z is an input/output data signal.

3 to 8 are partial detailed circuit diagrams for explaining the operation of this embodiment. FIG. 3 shows a row dummy cell group, FIG. 4 shows a column dummy cell group and a dummy column selector, and FIG. 5 shows a row dummy cell group. 6 shows a row decoder, FIG. 6 shows a column decoder, FIG. 7 shows a dummy row decoder, and FIG. 8 shows a dummy column decoder.

Next, the operation of this embodiment will be explained with reference to these figures.

In FIG. 2, the test column address buffer (BY) 17 is a dummy column decoder when a certain voltage higher than the power supply voltage is input to A _o among the address inputs A _p to A _o to the column decoder 12. 19
is active, the column decoder 12 outputs the signal DAY and its inverted signal so that all are unselected. Test address buffer (BX) 18
is from the address input A _o+1 to the row decoder 13.
Among A _n , when a certain voltage higher than the power supply voltage is input to A _n , the dummy row decoders 20 and 21
is active, the row decoder 13 outputs the signal DAX and its inverted signal so that all are unselected.

Now, consider a state in which a high voltage is input to the address input A _n and the dummy row decoders 20 and 21 are activated. In Figure 2, the dummy row decoder is 2
One of them is selected by address input A _o+1 . Dummy cell groups 23 and 24 driven by row lines selected by dummy row decoders 20 and 21 are arranged with memory cell matrix 16 in between.

FIG. 3 shows the row dummy cell group 23, 2 shown in FIG.
4 is a circuit diagram. For the memory cell matrix 16 consisting of M ₁₁ -M _xy , dummy cell groups 23, 2 consisting of DM ₁₁ -DM _1y and DM ₂₁ -DM _2y
4 are placed at both ends. Now, assume that column line d ₁₁ of column lines d ₁₁ to _{d 1y} is selected by column decoder 12. The sources (or drains) of memory cells M ₁₁ to M _x1 and dummy cells DM ₁₁ and DM ₂₁ , which are insulated gate field effect transistors having a floating gate structure, are commonly connected to the column line d ₁₁ . Further, each drain (or source) is commonly connected to the ground potential G, and their control gates are connected to a row decoder 13 or a dummy row decoder 20,
The row line which is the output of 21 is connected. In normal use, dummy cells DM ₁₁ and DM ₂₁ are ignored, and only memory cells M ₁₁ to M _x1 are activated. When used as a one-write EPROM,
The memory cells _M11 to _Mx1 are in an erased state, and in read-only checking, the level of column line _d11 is always checked only at a constant level. Furthermore, write function checks are completely ignored. Therefore, the dummy cells DM ₁₁ and DM ₂₁ are used to check the functions during writing and reading, and at least two dummy cells are provided for the column line d ₁₁ to check the conflicting data in DM ₁₁ and DM ₂₁ . write,
By reading, it is also possible to check the adverse effect that memory cells _M11 to _Mx1 have on the column line _d11 due to some defect. Also, between column lines d ₁₁ and d ₁₂ , dummy cells DM ₁₁ and DM ₁₂ , DM ₂₁ and
By writing contradictory data to DM ₂₂ , it is also possible to check for short circuits between column lines d ₁₁ and d ₁₂ , etc.
At the same time, it is also possible to check the circuit function of the column decoder system.

Subsequently, a high voltage is input to the address input A _o ,
Consider a state in which the dummy column decoder 19 becomes active. In FIG. 2, the dummy column decoder 19 is 1
The column dummy cell group 25 driven by the column line selected by the dummy column decoder 19 is arranged in the memory cell matrix 1.
6 are arranged in a row at one end.

FIG. 4 is a circuit diagram of the column dummy cell group shown in FIG. 2.

Dummy memory _cells DM _{1 to DM} is placed at one end of the
The source (or drain) of each cell in this column dummy cell group 25 is connected to the column line D _d selected by the dummy column decoder 19, and the drain (or source) of each cell is connected to the ground potential G.
The control gate of the cell is connected to the output of row decoder 13. Transistors Q ₁ ~ forming column selector 15 by normal column decoder outputs Y ₁₁ ~ Y _1y
Q _y selects one of the column lines d ₁ to d _y ,
Data is input and output. In this case, the column line D _d
The dummy cells DM ₁ to DM _x connected to the dummy column decoder 19 are ignored and not used because the output DY ₁ of the dummy column decoder 19 is not outputted to the gate of the transistor Q _d forming the dummy column selector. one light
When used as an EPROM, the memory cell matrix 16 is all in the erased state and the row decoder 1
The data selected and outputted by the output of 3 is read out only at a constant value in any case. Therefore, it is not possible to sufficiently check whether the decoder 13 is operating normally or whether there is a short circuit between row decoder outputs. Therefore, the output DY ₁ of the dummy column decoder 19
The row decoder 13 is set to "H" level to write and read data to column dummy cells _DM1 to _DMx connected to the column line _Dd .
and its output. By arranging at least one column of column dummy cell groups 25 selected by the dummy column decoder 19 for each input/output bit, efficient function checking can be performed by combining data of each input/output bit. Therefore, for input/output Z bits, a Z column of dummy cells is provided.

FIG. 5 is a circuit diagram of an example of the row decoder of the embodiment shown in FIG. 2.

In FIG. 5, number 26 is a row decoder output buffer. When the output from the test row address buffer 18 shown in FIG. 2 is at the "H" level, the row decoder becomes unselected because the transistor _QDX is turned on, and the row decoder enters the test mode. Therefore, the output is normally at the "L" level.

FIG. 6 is a circuit diagram of the column decoder 12. 6th
In the figure, 27 is a column decoder output buffer. When the output of the test column address buffer 17 is at the "H" level, the transistor _QDY turns on, so the column decoder becomes unselected and enters the test mode. Therefore, normally the output is “L”
It's getting to the level.

FIGS. 7 and 8 show dummy column decoders 20 and 21.
and a circuit diagram of a dummy column decoder 19. The outputs DAX and DAY of the test row address buffer 18 and the test column address buffer 17 are normally both at the "H" level, and the transistor Q _dx
and Q _dy are turned on, so they are in a non-selected state, but when the outputs DAX and DAY go to "L" level in the test mode, the output corresponding to the address input is selected. In FIG. 8, since the dummy cell group 25 in FIG. 2 is in one column, there is no address input, but if two or more columns are provided, as in FIG.
It can be selected by entering the address. In addition, 28,2
9 are a dummy row decoder output buffer and a dummy column decoder output buffer, respectively.

Note that although the above embodiment describes an N-channel type EPROM, it also applies to a P-channel type and a CMOS type.
Needless to say, this can be done in the same way for EPROM.

〔Effect of the invention〕

As described above in detail, the nonvolatile semiconductor memory of the present invention includes a test circuit consisting of a dummy cell group connected to row lines and column lines that are selected only during testing, and a peripheral circuit that selects the dummy cells. Therefore, even after the product is commercialized, it can be sufficiently tested, and it has the effect of providing a non-volatile semiconductor memory whose memory contents can be erased by high-speed, high-reliability ultraviolet irradiation, etc. . Therefore, the present invention is particularly effective when applied to a one-writing EPROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an example of a conventional nonvolatile semiconductor memory, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 3 to 8 are parts of FIG. 2, respectively. In the detailed circuit diagrams, Fig. 3 shows the row dummy cell group, Fig. 4 shows the column dummy cell group and dummy column selector, and Fig. 5 shows the row decoder.
7 is a detailed circuit diagram of a column decoder, FIG. 7 is a detailed circuit diagram of a dummy row decoder, and FIG. 8 is a detailed circuit diagram of a dummy column decoder. 1... Input/output controller, 2... Column decoder, 3... Row decoder, 4... Input/output buffer,
5... Column selector, 6... Memory cell matrix, 11... Input/output controller, 12... Column decoder, 13... Row decoder, 14... Input/output buffer, 15... Column selector, 16... Memory Cell matrix, 17...Test column address buffer (BY), 18...Test row address buffer (BX), 19...Dummy column decoder, 20,
21...Dummy row decoder, 22...Dummy column selector, 23, 24...Row dummy cell group, 25...
...Column dummy cell group, 26... Row decoder output buffer, 27... Column decoder output buffer, 28...
...Dummy row decoder output buffer, 29...Dummy column decoder output buffer, A _p - A _n ... Address input, C ... Control signal, ₀ - ₇ , O _z ... Input/output data signal, X ₁₁ - X _1x ...Row decoder output signal, _Y11 to _Y1y ...Column decoder output signal, _DX1 ,
DX ₂ ...Dummy row decoder output signal, DY ₁ ...Dummy column decoder output signal, _M11 ~A _xy ...Memory cell, _DM11 ~ _DM1y , _DM21 ~ _DM2y , _DM1 ~
_DM2 ...Dummy memory cell, _d11 ~ _d1y , Dd...
Column line, DAX,, DAY, ...Test address buffer output, V _cc ...Power supply voltage, G...
Ground potential, Q ₁ , Q ₂ , Q _y , Q _d , Q _DX , Q _DY , Q _dx ,
Q _dY ...N-channel MOS transistor.

Claims (1)

[Scope of Claims] 1. A memory cell matrix that includes a plurality of memory cells arranged in row and column directions, writes normal data to a specified address, and reads data from a specified address; It is provided with a plurality of dummy cells corresponding to the memory cells in the row direction of the memory cell matrix, and is provided across the memory cell matrix, and writes test data to a specified address when in a selected state, and writes test data to the specified address. a plurality of dummy cells corresponding to memory cells in the column direction of the memory cell matrix; and a plurality of dummy cells for reading data from and to the memory cell matrix. are provided corresponding to each bit of the read data,
A plurality of column dummy cell groups in which test data is written to a specified address when in a selected state and data is read from a specified address; and the memory cell matrix and column dummy cell group in response to a first address input when activated. a column decoder and a column selector that, when activated, specify a column address of the memory cell matrix and row dummy cells by a second address input; a dummy row decoder that selects one of the groups; a dummy column decoder and a dummy column selector that selects the column dummy cell group when activated; When the specific bit is at a predetermined level equal to or higher than the power supply voltage, the dummy row decoder is activated and the row decoder is deactivated, and when the specific bit is at a normal logic level lower than the power supply voltage, the dummy row decoder is activated. a test row address buffer that deactivates the row decoder and activates the row decoder; and the dummy column decoder when a specific bit of the second address input is at a predetermined level equal to or higher than the power supply voltage. and a dummy column selector are activated, and the column decoder and column selector are inactivated, and when a specific bit of the second address input is at a normal logic level below the power supply voltage, the dummy column decoder and the column selector are activated. A test column address buffer that deactivates the dummy column selector and activates the column decoder and column selector, and data for writing to the memory cell matrix, row dummy cell group, and column dummy cell group. 1. A nonvolatile semiconductor memory comprising an input/output buffer for transmitting data and outputting data read from the memory cell matrix, the row dummy cell group, and the column dummy cell group to the outside. 2. The nonvolatile semiconductor memory according to claim 1, wherein the dummy cell is an insulated gate field effect transistor having a floating gate structure identical to that of the memory cell of the memory cell matrix.