JPH01276915A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPH01276915A JPH01276915A JP63106118A JP10611888A JPH01276915A JP H01276915 A JPH01276915 A JP H01276915A JP 63106118 A JP63106118 A JP 63106118A JP 10611888 A JP10611888 A JP 10611888A JP H01276915 A JPH01276915 A JP H01276915A
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- channel mos
- inverter
- mos transistor
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路で実現された論理回路に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit realized with a semiconductor integrated circuit.
従来の半導体集積回路における論理回路の一実繕例を示
す回路図を第２図に示す、これは、一般にＳＲ型ラフリ
ップフロップ呼ばれているが、第２図に示すように第１
の入力端子１を第１の２人力ＮＯＲ回路８の入力端子８
ａに接続し、第１の２人力ＮＯＲ回路８の出力端子１１
を出力端子１２と第２の２人力ＮＯＲ回路９の入力端子
９ａに接続し、第２の入力端子２を第２の２人力ＮＯＲ
回路９の入力端子９ｂに接続し、第２の２人力ＮＯＲ回
路９の出力端子１０を第１゛の２人力ＮＯＲ回路８の入
力端子８ｂに接続して構成されていた。FIG. 2 shows a circuit diagram showing an example of a logic circuit in a conventional semiconductor integrated circuit.This is generally called an SR type rough flip-flop, but as shown in FIG.
input terminal 1 of the input terminal 8 of the first two-person NOR circuit 8
a, and the output terminal 11 of the first two-power NOR circuit 8
is connected to the output terminal 12 and the input terminal 9a of the second two-manpower NOR circuit 9, and the second input terminal 2 is connected to the second two-manpower NOR circuit 9.
It was connected to the input terminal 9b of the circuit 9, and the output terminal 10 of the second two-manpower NOR circuit 9 was connected to the input terminal 8b of the first two-manpower NOR circuit 8.
上記の論理回路は、第１の入力端子１が論理値で１″で
、第２の入力端子２が論理値で“Ｏ”のときは、出力端
子１２が論理値で“０”となり、第１の入力端子１が論
理値で“０”で、第２の入力端子２が論理値で“１″の
ときは、出力端子１２が論理値“１ｎとなり、第１の入
力端子１が論理値で“０”で、第２の入力端子２が論理
値で“０″のときは、出力端子１２は前の状態を保持し
、第１の入力端子１が論理値で“１”で、第２の入力端
子２が論理値で“１”となるように入力することは、禁
止するようになっていた。In the above logic circuit, when the first input terminal 1 has a logical value of 1" and the second input terminal 2 has a logical value of "O", the output terminal 12 has a logical value of "0", and the second input terminal 2 has a logical value of "0". When the input terminal 1 of the first input terminal 1 has a logical value of "0" and the second input terminal 2 has a logical value of "1", the output terminal 12 has a logical value of "1n", and the first input terminal 1 has a logical value of "1". is "0" and the second input terminal 2 has a logical value of "0", the output terminal 12 maintains the previous state, and the first input terminal 1 has a logical value of "1" and the It was prohibited to input an input so that the input terminal 2 of No. 2 would have a logical value of "1".
上述した従来の論理回路は２人力ＮＯＲ回路を２個用い
ているため、トランジスタ数が多くチ・ノブ面積が大き
くなるという欠点がある。Since the above-mentioned conventional logic circuit uses two two-way NOR circuits, it has the disadvantage that the number of transistors is large and the chi-knob area becomes large.
本発明の目的は前記課題を解決した論理回路を提供する
ことにある。An object of the present invention is to provide a logic circuit that solves the above problems.
上記目的を達成するため、本発明の論理回路は、第１の
入力端子をＰチャンネル型ＭＯＳトランジスタのゲート
電極に接続し、該Ｐチャンネル型ＭＯＳトランジスタの
ソース電極を正電源に接続し、該Ｐチャンネル型ＭＯＳ
トランジスタのドレイン電極を第１のインバータの入力
端子に接続し、第２の入力端子をＮチャンネル型ＭＯ３
）ランジスタのゲート電極に接続し、該Ｎチャンネル型
ＭＯＳトランジスタのソース電極を負電源に接続し、該
Ｎチャンネル型ＭＯＳトランジスタのドレイン電極を該
第１のインバータの入力端子に接続し、該第１のインバ
ータの出力端子を出力端子と第２のインバータの入力端
子に接続し、該第２のインバータの出力端子を該第１の
インバータの入力端子に接続して構成したものである。In order to achieve the above object, the logic circuit of the present invention connects a first input terminal to a gate electrode of a P-channel MOS transistor, connects a source electrode of the P-channel MOS transistor to a positive power supply, and connects a first input terminal to a gate electrode of a P-channel MOS transistor. Channel type MOS
The drain electrode of the transistor is connected to the input terminal of the first inverter, and the second input terminal is connected to the N-channel type MO3
) connected to the gate electrode of the transistor, the source electrode of the N-channel MOS transistor connected to a negative power supply, the drain electrode of the N-channel MOS transistor connected to the input terminal of the first inverter; The output terminal of the inverter is connected to the output terminal and the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
図において、本発明の論理回路は、第１の入力端子１を
Ｐチャンネル型ＭＯＳトランジスタ３のゲート電極に接
続し、Ｐチャンネル型ＭＯＳトランジスタ３のソース電
極を正電源に接続し、Ｐチャンネル型ＭｏＳトランジス
タ３のドレイン電極を第１のインバータ５の入力端子に
接続し、第２の入力端子をＮチャンネル型ＭＯＳトラン
ジスタ４のゲート電極に接続し、Ｎチャンネル型ＭＯＳ
トランジスタ４のソース電極を負電源に接続し、Ｎチャ
ンネル型ＭＯＳトランジスタ４のドレイン電極を第１の
インバータ５の入力端子に接続し、第１のインバータ５
の出力端子を出力端子７と第２のインバータ６の入力端
子に接続し、第２のインバータ６の出力端子を第１のイ
ンバータ５の入力端子に接続して構成している。In the figure, the logic circuit of the present invention connects the first input terminal 1 to the gate electrode of a P-channel MOS transistor 3, connects the source electrode of the P-channel MOS transistor 3 to a positive power supply, and connects the first input terminal 1 to the gate electrode of a P-channel MOS transistor 3. The drain electrode of the transistor 3 is connected to the input terminal of the first inverter 5, and the second input terminal is connected to the gate electrode of the N-channel type MOS transistor 4.
The source electrode of the transistor 4 is connected to a negative power supply, the drain electrode of the N-channel MOS transistor 4 is connected to the input terminal of the first inverter 5, and the first inverter 5
The output terminal of the inverter 6 is connected to the output terminal 7 and the input terminal of the second inverter 6, and the output terminal of the second inverter 6 is connected to the input terminal of the first inverter 5.
上記の論理回路は、第１の入力端子１が論理値で“０″
で、第２の入力端子２が論理値で“０”のときは、Ｐチ
ャンネル型ＭＯＳトランジスタ３がオン状態になり、Ｎ
チャンネル型ＭＯＳトランジスタ４がオフ状態となるの
で、第１のインバータ５の入力端子は論理値で“１″と
なり、出力端子７に論理値で“０”を出力し、第１の入
力端子１が論理値で“１″で第２の入力端子２が論理値
で“１”のときは、Ｐチャンネル型ＭＯＳトランジスタ
３がオフ状態になり、Ｎチャンネル型ＭＯＳトランジス
タ４がオン状態となるので、第１のインバータ５の入力
端子は論理値で“０″となり、出力端子７に論理値で“
１″を出力する。また、第１の入力端子１が論理値で“
１″で第２の入力端子２が論理値で“０”のときは、Ｐ
チャンネル型ＭＯＳトランジスタ３がオフ状態になり、
Ｎチャンネル型ＭＯＳトランジスタ４もオフ状態となる
ので第１のインバータ５と第２のインバータ６の作用に
より前の状態を保持し、その値を出力端子７に出力する
。一方、第１の入力端子１が論理値で“Ｏ”で第２の入
力端子２が論理値で“１″のときは、Ｐチャンネル型Ｍ
ＯＳトランジスタ３がオン状態になり、Ｎチャンネル型
ＭＯＳトランジスタ４もオン状態となるので入力禁止と
している。このようにして、ＳＲ型フリップフロップと
同等の機能を実現している。In the above logic circuit, the first input terminal 1 has a logic value of “0”.
When the second input terminal 2 has a logical value of "0", the P-channel type MOS transistor 3 is turned on, and the N
Since the channel type MOS transistor 4 is turned off, the input terminal of the first inverter 5 has a logic value of "1", outputs a logic value of "0" to the output terminal 7, and the first input terminal 1 becomes When the logic value is "1" and the second input terminal 2 has a logic value of "1", the P-channel MOS transistor 3 is turned off and the N-channel MOS transistor 4 is turned on. The input terminal of inverter 5 of No. 1 has a logical value of “0”, and the output terminal 7 has a logical value of “0”.
1'' is output. Also, the first input terminal 1 is a logical value and outputs “
1" and the second input terminal 2 has a logical value of "0", P
Channel type MOS transistor 3 is turned off,
Since the N-channel MOS transistor 4 is also turned off, the previous state is maintained by the action of the first inverter 5 and the second inverter 6, and its value is output to the output terminal 7. On the other hand, when the first input terminal 1 has a logical value of "O" and the second input terminal 2 has a logical value of "1", the P-channel type M
Since the OS transistor 3 is turned on and the N-channel MOS transistor 4 is also turned on, input is prohibited. In this way, a function equivalent to that of an SR type flip-flop is realized.
以上説明したように本発明によれば、トランジスタの数
を減らすことができ、チップ面積を小さくできる効果が
ある。As explained above, according to the present invention, it is possible to reduce the number of transistors and the chip area can be reduced.
第１図は本発明の論理回路の一実施例を示すブロック図
、第２図は従来の論理回路を示すプロッり図である。
１・・・第１の入力端子 ２・・・第２の入力端子
３・・・Ｐチャンネル型ＭＯＳトランジスタ４・・・Ｎ
チャンネル型ＭＯ３）ランジスタ５・・・第１のインバ
ータ ６・・・第２のインバー７・・・出力端子FIG. 1 is a block diagram showing an embodiment of the logic circuit of the present invention, and FIG. 2 is a plot diagram showing a conventional logic circuit. 1...First input terminal 2...Second input terminal 3...P channel type MOS transistor 4...N
Channel type MO3) transistor 5...first inverter 6...second inverter 7...output terminal
Claims (1)
ャンネル型ＭＯＳトランジスタのゲート電極に接続し、
該Ｐチャンネル型ＭＯＳトランジスタのソース電極を正
電源に接続し、該Ｐチャンネル型ＭＯＳトランジスタの
ドレイン電極を第１のインバータの入力端子に接続し、
第２の入力端子をＮチャンネル型ＭＯＳトランジスタの
ゲート電極に接続し、該Ｎチャンネル型ＭＯＳトランジ
スタのソース電極を負電源に接続し、該Ｎチャンネル型
ＭＯＳトランジスタのドレイン電極を該第１のインバー
タの入力端子に接続し、該第１のインバータの出力端子
を出力端子と第２のインバータの入力端子に接続し、該
第２のインバータの出力端子を該第１のインバータの入
力端子に接続して構成したことを特徴とする論理回路。(1) In a semiconductor integrated circuit, a first input terminal is connected to a gate electrode of a P-channel MOS transistor,
A source electrode of the P-channel MOS transistor is connected to a positive power supply, a drain electrode of the P-channel MOS transistor is connected to an input terminal of a first inverter,
A second input terminal is connected to the gate electrode of the N-channel MOS transistor, a source electrode of the N-channel MOS transistor is connected to a negative power supply, and a drain electrode of the N-channel MOS transistor is connected to the first inverter. an output terminal of the first inverter is connected to an output terminal and an input terminal of a second inverter, and an output terminal of the second inverter is connected to an input terminal of the first inverter. A logic circuit characterized by being configured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63106118A JPH01276915A (en) | 1988-04-28 | 1988-04-28 | Logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63106118A JPH01276915A (en) | 1988-04-28 | 1988-04-28 | Logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01276915A true JPH01276915A (en) | 1989-11-07 |
Family
ID=14425536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63106118A Pending JPH01276915A (en) | 1988-04-28 | 1988-04-28 | Logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01276915A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006287906A (en) * | 2005-03-31 | 2006-10-19 | Hynix Semiconductor Inc | Data latch circuit of semiconductor device |
| JP2007184925A (en) * | 2005-12-30 | 2007-07-19 | Infineon Technologies Ag | Pulsed static flip-flop |
| JP2009206760A (en) * | 2008-02-27 | 2009-09-10 | Seiko Instruments Inc | Delay circuit |
| JP2011147165A (en) * | 2001-06-30 | 2011-07-28 | Hynix Semiconductor Inc | Semiconductor device equipped with register control delay lock loop |
| JP2012257188A (en) * | 2010-08-25 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | Latch circuit and semiconductor device |
-
1988
- 1988-04-28 JP JP63106118A patent/JPH01276915A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011147165A (en) * | 2001-06-30 | 2011-07-28 | Hynix Semiconductor Inc | Semiconductor device equipped with register control delay lock loop |
| JP2006287906A (en) * | 2005-03-31 | 2006-10-19 | Hynix Semiconductor Inc | Data latch circuit of semiconductor device |
| JP2007184925A (en) * | 2005-12-30 | 2007-07-19 | Infineon Technologies Ag | Pulsed static flip-flop |
| US8188780B2 (en) | 2005-12-30 | 2012-05-29 | Infineon Technologies Ag | Pulsed static flip-flop |
| JP2009206760A (en) * | 2008-02-27 | 2009-09-10 | Seiko Instruments Inc | Delay circuit |
| JP2012257188A (en) * | 2010-08-25 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | Latch circuit and semiconductor device |
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