JPH02274119A - Set/reset flip-flop circuit - Google Patents

Abstract

PURPOSE:To reduce the number of transistor(TR) elements by connecting series circuit of complementary 1st and 2nd MOS TRs in series with a 3rd MOS TR to constitute a set priority reset flip-flop circuit. CONSTITUTION:A set priority reset flip-flop circuit consists of the series connection between a P-channel MOS TR 1 and N-channel MOS TRs 2, 3. That is, the gate of the TR 1 and the gate of the TR 2 are connected and its connecting point is used as an input terminal inverse of S, and the gate of the TR 3 is used as an input terminal R. The source of the TR 1 connects to a power supply VDD, the source of the TR 2 and the drain of the TR 3 are connected in common and the source of the TR 3 connects to ground (VSS). The drain of the TR 1 and the source of the TR 2 are connected in series and its connecting point is used as an output terminal Q. Thus, the number of TR components is decreased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a set-reset flip-flop circuit,
In particular, in the dynamo circuit (FIG. 5) including CMOS transistors, the outputs of the two NAND circuits 31 and 32 are connected to the inputs of the other NAND circuit, and the other input is connected to the S (set) input and the R (reset) input. , output '1i=Q output, Q output. In Table 5,
In case of SR large input [0°O], QQ output is (1,,1)
When the SR large input is (0, 1) or (1, 0), the QQ output is CX, 0) or (0, 1], and the set state or reset state is set. , 1], the QQ output retains the previous state and there is no new change, resulting in a so-called holding state.

Here, the inhibit input signal S=ゝ0'', 几=ゝゝ0''
The set priority circuit depends on whether it is in the set state or in the reset state when n is input.

There is a reset priority circuit, shown in FIGS. 6 and 7, respectively. In addition, the operational functions of the priority circuits in Figures 6 and 7 based on positive logic are shown in Tables 6 and 7, respectively, using two-man power N A and ND similar to those in Figure 5.
In addition to the circuits 33 and 34, a two-man OR circuit 38 and an inverter 37 are added. This set priority circuit is 81 (
- When the input is (0, 0), the QQ output is [1, 0:l, which is the set priority state (Table 6).

Other functions are the same as in Table 5.

In FIG. 7, O
A converter circuit 39 is interposed, and an inverter 40 is interposed between this other input and the R input. This reset priority circuit is S
In the case of R large input [o, o), the QQ output is in the reset state of [0, 1:) (Table 7).Other functions are the same as in Table 5.

FIG. 8 is a circuit diagram showing the conventional SFF circuit of FIG. 5 at the transistor level. In FIG. 8, it consists of a P-channel MOS transistor 16.17°18.19 and an n-channel+MOS transistor 20°21.22.23. N consisting of transistors 16°17.20.22
The so-called "crossing" of the AND circuit and the N A and N0 circuits consisting of transistors 18, 19, 21, and 23.
Consists of.

FIG. 9 is a circuit diagram showing the conventional set priority R8FF circuit of FIG. 6 at the transistor level.

In FIG. 9, P channel MO8I-transistor 24
．． 25.26 and N-channel M (JS transistor 27.
It consists of 28.29.

The conventional priority circuit mentioned above is a cross-connected SRF P of NAND gates, an inverter, an OR, a gate configuration state, and a Rina circuit.

[Problem to be solved by the invention]

Both of the conventional S1 (1F F7) mentioned above have logic gates cross-connected, and feedback is applied by a static circuit, so they have a large number of transistor elements, and if they are used as a priority circuit, they will be connected to an inverter (JR gate). is added, and the number of transistor elements also increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a set-reset flip-flop circuit in which the above drawbacks are overcome and the number of transistor elements can be reduced.

[Means to solve the problem]

The configuration of the set-reset flip-flop circuit of the present invention includes first . The second series body of MOS transistors and the third MO8I-transistor are connected in series, and the first MOS transistor is connected in series. connected between the second power source and the first power source; The gates of the second MOS transistors are commonly connected to each other to serve as the first input, the series connection point of the first and second MOS transistors is used as the output, and the third MOS transistor is used as the second input. It is characterized by what it did.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a set priority RS FF circuit according to an embodiment of the present invention. In FIG. 1, 1 of this embodiment is also SFF
The circuit is made up of a Pg-Yannel Mos transistor 1 and N-channel MO8 transistors 2 and 3 connected in series.

The gate electrode of the transistor 1 and the gate electrode of the transistor 2 are connected, the connection point thereof is designated as an input terminal S, and the gate electrode of the transistor 30 is designated as an input terminal. The source electrode of transistor l is connected to the power supply VDD, the source electrode of transistor 2 and the drain electrode of transistor 3 are commonly connected, and the source electrode of transistor 3 is connected to ground (V
ss) has been done. The drain pole of the transistor l and the source electrode of the transistor 2 are connected in series, and the connection point is defined as an output terminal Q.

Next, the operation will be explained in terms of positive logic using Table 1.

When S is at %%Q" level and 几 is at 10" level, the transistor is on, transistors 2 and 3 are off, and the output QFi is at 1" level, resulting in a set state of 1.S is '
Q" level, when R is "1" level, transistor 1
is on, transistor 2 is off, transistor 3 is on, and the output Q is 11", which is the set state.
When is at the "L#" level and 几 is at the "Q" level, transistor 1 is off, transistor 2 is on, and transistor 3 is off, and the output Q does not change. S is 11 “Lehe A/
When the R signal is at the "1" level, the transistor 1 is on, the transistor 2 is off, the transistor 3 is on, and the output Q is O, resulting in a reset state.

By the way, FIG. 3 is a circuit diagram showing a dynamic SR flip-flop circuit, and its operational function table is shown in Table 3 below.

In FIG. 3, output Q is a common connection point between the drains of p and n MO8 transistors 7 and 8 which are complementary to each other.

Table 3 As can be seen by comparing Table 3 with Table 1, the prohibited state in FIG. 1 is not a set state, and the circuit in FIG. 1 is a set priority circuit.

FIG. 2 is a circuit diagram of a set-reset flip-flop circuit according to another embodiment of the present invention. In FIG. 2, the reset priority 5RIFF circuit of this embodiment is a P-channel MC)
It is configured to include S transistors 4 and 5 and an N channel MOS transistor 6.

The gate electrode of transistor 4 is set as input terminal S, the gate electrodes of transistors 5 and 6 are commonly connected, and the connection point is set as input terminal S. The source electrode of the transistor 4 is connected to the power supply VDD, the drain electrode of the transistor 4 and the source electrode of the transistor 5 are connected in series,
The source electrode of transistor 6 is grounded (Vss). The source electrode of transistor 5 and the transistor 6
are commonly connected to the drain electrodes, and the connection point is set as the output terminal Q.

Next, the operation will be explained in terms of positive logic using Table 2.

When S is at 90'' level and R is at O'' level, transistor 4 is on, transistor 5 is on, and transistor 6 is on.
turns off, the output Q becomes ``1'', and is in the set state. When S is at the ``O'' level and the other is at the ``L'' level, transistor 4 is on, transistor 5 is off, and transistor 6 is on. Otherwise, the output Q becomes 0, and a reset state is entered.

When 8 is at 91" level and R is at 0" level, transistor 4 is off, transistor 5 is on, and transistor 6 is off, and there is no change. When S is at the "1" level and R- is at the "1" level, the reset state is established. These operating function tables are shown in Table 2. In FIG. 2, it can be seen that the prohibited state in Table 3 becomes a reset state and becomes a reset priority circuit.

In this embodiment, since it is a dynamic circuit at the fl1 point where it is stabilized in the reset state when the inhibit input signal is input, there is an advantage that the number of transistor elements is small and they are adjacent to each other.

FIG. 4 shows set priority S R of still another embodiment of the present invention.
FIG. 2 is a circuit diagram showing an FP circuit. In FIG. 4, P channel MO8) run raster 11. N-channel MO8 transistors 12 and 13 are connected in series, a P-channel MOS transistor 9 and an N-channel MO8 transistor 10 are connected in series, and further, P and N-channel MO8 transistors 14 and 15 are connected in series, and each is connected to the power supply VDD and ground. is connected between.

The operation of this circuit is similar to that shown in Table 1 above.

〔Effect of the invention〕

As explained above, the present invention has the effect of preventing through current at the time of inhibit input by providing a set (or reset) priority circuit, and the conventional priority circuit
As shown in Figures and Figure 9, 14 CMOS transistors are used, but these can be configured with 7, which reduces the number of transistor elements, making the circuit simpler and the wiring less complicated. There is an effect.

[Brief explanation of drawings]

FIG. 1 shows a set priority 81 (,FFl) according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing the 81 (, FF) in Figure 1 with reset priority, Figure 3 is a circuit diagram of a dynamic S-FF, Figure 4 is a circuit diagram with set priority in Figure 1. A circuit in which an output inversion terminal Q and a manual inversion terminal S are added to the S-FF circuit. Figure 5 is a circuit diagram of a conventional S-FF circuit, and Figure 6 is a circuit diagram of a conventional set-priority 5RFP circuit. FIG. 7 is a circuit diagram of a conventional reset priority S-type FF circuit, FIG. 8 is a circuit diagram showing the conventional 5RFP circuit of FIG. 5 at the transistor level, and FIG. 9 is a circuit diagram of a conventional set-priority S It is a circuit diagram showing the NOB gate and inverter section of the FF circuit at the transistor level.VDD...Power supply, S, S, 几...Input terminal, Q.Q... ...Output terminal, 1, 4, 5, 7, 9
, 11, 14°16 to 19.24 to 26...
...P channel transistor, 2, 3, 6, 8, 10
,12,13゜15.20,21,22,23,27,
28.29...N channel transistor, 31
,32,33゜34.35.36...NAND
Circuit, 38, 39...OR circuit, 37, 40...
...Inverter. Agent Patent Attorney Hara Uchihara

Claims (1)

[Claims] A series body of first and second MOS transistors that are complementary to each other and a third MOS transistor are connected in series, and the first
, connected between a second power supply, and the gates of the first and second MOS transistors are connected in common to serve as a first input;
A set-reset flip-flop circuit characterized in that a series connection point of the first and second MOS transistors is used as an output, and a gate of the third MOS transistor is used as a second input.