JPH04361421A - Two phase clock generating circuit - Google Patents

Abstract

PURPOSE:To reduce the chip area in the case of circuit integration with less number of elements. CONSTITUTION:An input clock signal is inputted to a PMOS 7 and NMOS 9, outputted from an output terminal B, and the input clock signal is inputted to PMOS 4 and an NMOS 3 via an inverter 30, outputted from an output terminal C, and a PMOS 8 and an NMOS 5 connecting the output terminals B,C to a power supply 20 in response to an output of other output terminal mutually to form the two phase clock generating circuit with PMOS 4,5,7,8 and the NMOS 3,9 in addition to the PMOS 1 and the NMOS 2 constituting the inverter 30.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-phase clock generation circuit that generates two-phase clock signals based on one clock signal, and relates to a two-phase clock generation circuit used in digital signal processors and the like.

0002

2. Description of the Related Art FIG. 2 shows a circuit diagram of a conventional two-phase clock generation circuit. In the figure, A is an input terminal, and B and C are first and second output terminals, respectively. 1, 4, 5, 7, 8 are P
Channel MOS transistor (hereinafter abbreviated as PMOS)
, 2, 3, 6, 9, and 10 are N-channel MOS transistors (hereinafter abbreviated as NMOS), and PMOS1 and NM
OS2 constitutes a CMOS inverter 30. The PMOS 1 has a source connected to a power supply 20 having a positive potential, and a gate connected to an input terminal A. The source of NMOS2 is grounded, the drain is connected to the drain of PMOS1, and the gate is connected to the gate of PMOS1. PMOS
4 has the source connected to the power supply 20, and the gate connected to PMOS1 and NMO.
The drains are respectively connected to the second output terminal C at the drain common connection point of S2. NMOS3 and NMOS6 are connected in series between the second output terminal C and the ground point, the gate of NMOS3 is connected to the common drain connection point of PMOS1 and NMOS2, and the gate of NMOS6 is connected to the first output terminal B. are connected to each. PMOS5 has a source connected to the power supply 20, a gate connected to the first output terminal B, and a drain connected to the second output terminal B.
are connected to the output terminals C of the respective terminals. The PMOS 7 has a source connected to the power supply 20, a gate connected to the input terminal A, and a drain connected to the first output terminal B. The PMOS 8 has a source connected to the power supply 20, a gate connected to the second output terminal C, and a drain connected to the first output terminal B. N.M.O.
S9 and S10 are connected in series between the first output terminal B and the ground point, and the gate of NMOS9 is connected to the input terminal A.
The gates of the NMOSs 10 are each connected to a second output terminal C.

Next, the operation will be explained. When “L” is input to input terminal A, PMOS1 and 7 are turned on, and NM
OS2 and OS9 are turned off. PMOS1 is ON, NMOS
2 is OFF, the potential of node X becomes "H". In response to this “H”, PMOS4 turns OFF and NMOS3
turns on. Also, PMOS7 is ON and NMOS9 is OFF.
Since it is an FF, "H" is output to the first output terminal B. In response to this “H”, PMOS5 is turned off and NM
Since the OS6 is turned on, "L" is output to the second output terminal C.

On the other hand, when "H" is input to input terminal A, PMOS1 and 7 are turned off and NMOS2 and 9 are turned on. Since PMOS1 is OFF and NMOS2 is ON, the potential of node X becomes "L". In response to this “L”, PM
Since OS4 is turned on and NMOS3 is turned off, "H" is output to the second output terminal C. In response to this "H", PMOS8 is turned off and NMOS10 is turned on. Furthermore, since PMOS7 is OFF and NMOS9 is ON, "L" is output to the first output terminal B.

As described above, when "L" is input to input terminal A, "H" and "L" are input to first and second output terminals B and C.
is output, and when "H" is input to input terminal A, "L" and "H" are output to the first and second output terminals B and C, so the clock signal to input terminal A is A two-phase clock signal can be generated.

[0006]

[Problems to be Solved by the Invention] The conventional two-phase clock generation circuit is configured as described above, and requires at least 10 transistors to be used. However, there was a problem in that the chip area increased.

The present invention has been made to solve the above-mentioned problems, and its object is to obtain a two-phase clock generation circuit with a small number of elements.

[0008]

[Means for Solving the Problems] A two-phase clock generation circuit according to the present invention inputs a clock input to a first PMOS and a third NMOS, outputs the output to a first output terminal, and also outputs a clock input to a first PMOS and a third NMOS. is input to the fourth PMOS and sixth NMOS via a CMOS inverter, and the output thereof is output to the second output terminal, and the first and second output terminals are connected to each other according to the output of the other output terminal. By providing a second PMOS and a fifth NMOS connected to the potential of
The circuit is configured with a total of eight transistors, five PMOS and three NMOS.

[0009]

[Operation] The two-phase clock generation circuit in this invention is PM
Since the circuit is composed of 5 OSs and 3 NMOSs, the number of elements is smaller than that of conventional circuits.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a two-phase clock generation circuit according to an embodiment of the present invention. In the figure, the difference from the conventional circuit shown in FIG. 2 is that NMOS 6 and 10 are eliminated. The other configurations are the same as the conventional one, 1.
2 are PMOS and NMOS constituting the CMOS inverter 30; 4, 5, 7, and 8 are fourth, fifth, and fourth transistors of the first conductivity type;
PMOS as the first and second transistors, NMO as the sixth and third transistors 3 and 9 of the second conductivity type
It is S.

Next, the operation will be explained. When “L” is input to input terminal A, PMOS1 and 7 are turned on and NMO
S2 and S9 are turned off. PMOS1 is ON, NMOS2
Since is OFF, the potential of node X becomes "H". this"
In response to “H”, NMOS3 turns on and PMOS4 turns off.
do. Since PMOS7 is ON and NMOS9 is OFF, "H" is output to the first output terminal B. In response to this "H", PMOS5 is turned off. PMOS4 is OFF
, since NMOS3 is ON, the second output terminal C is “L”
is output.

On the other hand, when "H" is input to input terminal A, PMOS1 and 7 are turned off and NMOS2 and NMOS9 are turned on. Since PMOS1 is OFF and NMOS2 is ON, the potential of node X becomes "L". In response to this “L”, NM
Since OS3 is OFF and PMOS4 is ON, "H" is output to the second output terminal C. In response to this "H", PMOS8 is turned off. PMOS7 is OFF, N
Since MOS9 is ON, "L" is output to the first output terminal B.

As described above, when "L" is input to input terminal A, "H" and "L" are input to first and second output terminals B and C.
is output, and when "H" is input to input terminal A, "L" and "H" are output to the first and second output terminals B and C, so the clock signal to input terminal A is A two-phase clock signal can be generated.

As described above, according to the two-phase clock generation circuit according to this embodiment, the input clock signal is input to the first PMO.
The input clock signal is input to S7 and the third NMOS 9 and its output is output to the first output terminal B, and the input clock signal is input to the fourth PMOS 4 and the sixth NMOS 3 via the CMOS inverter 30 and output therefrom. the second output terminal C
a second PMO that connects the first and second output terminals B and C to the power supply 20 according to the output of the other output terminal;
By providing S8 and the fifth NMOS5, in addition to the PMOS1 and NMOS2 that constitute the inverter 30, the PMOS
The circuit is composed of six transistors: S4, 5, 7, 8 and NMOS 3, 9, so the number of elements is smaller than the conventional one, and when integrated, the chip area is reduced. be.

Note that the conductivity types shown in the above embodiments may be reversed. In this case, it is also necessary to reverse the power supply 20 and ground potential.

[0016]

As described above, according to the two-phase clock generation circuit according to the present invention, a clock input is input to the first transistor of the first conductivity type and the third transistor of the second conductivity type. The output is outputted to the first output terminal, and the clock input is inputted to the fourth transistor of the first conductivity type and the sixth transistor of the second conductivity type via the CMOS inverter, and the output is inputted to the second output terminal. a second transistor of the first conductivity type and a fifth transistor of the second conductivity type, each of which connects the first and second output terminals to the first potential according to the output of the other output terminal; This allows the circuit to consist of a total of 8 transistors, 5 transistors of the first conductivity type and 3 transistors of the second conductivity type, which reduces the number of elements compared to the conventional method and facilitates integration. In some cases, this has the effect of reducing the chip area.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a two-phase clock generation circuit according to the present invention.

FIG. 2 is a circuit diagram showing a conventional two-phase clock generation circuit.

[Explanation of symbols]

A Input terminal B First output terminal C Second output terminal 1 PMOS transistor 2 NMOS transistor 3 NMOS transistor 4 PMOS transistor 5 PMOS transistor 7 PMOS transistor 8 PMOS transistor 9 NMOS transistor 20 Power supply 30 CMOS inverter

Claims (1)

[Claims] 1. An input terminal into which one type of clock is input, a control electrode connected to the input terminal, a first electrode connected to a first potential, and a second electrode connected to a first output terminal. a first transistor of a first conductivity type, a control electrode connected to a second output terminal, a first electrode connected to the first potential, and a second electrode connected to the first output terminal. a second transistor of a first conductivity type; a second conductivity type transistor having a control electrode connected to the input terminal, a first electrode connected to the first output terminal, and a second electrode connected to a second potential; an inverter having an input connected to the input terminal, a control electrode connected to the output of the inverter, a first electrode connected to the first potential, and a second electrode connected to the second output. a fourth transistor of a first conductivity type connected to the terminals, a control electrode connected to the first output terminal, a first electrode connected to the first potential, and a second electrode connected to the second output terminal; a fifth transistor of a first conductivity type connected to the terminals, a control electrode connected to the output of the inverter, a first electrode connected to the second output terminal, and a second electrode connected to the second potential; A two-phase clock generation circuit comprising: sixth transistors of a second conductivity type connected to each other.