JP2000101415A - Cmos buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a through-current with fewer number of components than those of a conventional circuit. SOLUTION: An input signal is respectively given to a gate of a 4th P-channel CMOS transistor(TR) 4, configuring an output stage via a 1st P-channel CMOS TR 1 and to a gate of a 4th N-channel CMOS TR 8, configuring the output stage via a 1st N-channel CMOS TR 5. A gate voltage of the 4th N-channel CMOS TR 8 is fed back to the gate of the 1st P-channel CMOS TR 1, and a gate voltage of the 4th P-channel CMOS TR 4 is fed back to the gate of the 1st N-channel CMOS TR 5 respectively, so as to suppress the through- current that flows through the 4th P-channel CMOS TR 4 and the 4th N-channel CMOS TR 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called CMOS
The present invention relates to a buffer circuit having (Complementary MOS) transistors, and more particularly, to a buffer circuit that suppresses a so-called through current.

[0002]

2. Description of the Related Art Conventionally, as a circuit of this kind, for example,
Some have a configuration as shown in FIG. Hereinafter, the configuration and operation of the CMOS buffer circuit will be generally described with reference to FIG.
It comprises a fifth P-channel CMOS transistor MP5 and a fifth N-channel CMOS transistor MN5 connected in series between the power supply and the ground. The gates of these two transistors MP5 and MN5 and the input terminal 22 are connected to each other. Between them, an OR circuit 20 as described below
And an AND circuit 21 are provided.
That is, the OR circuit 20 includes the first and second P-channel CMOS transistors MP1 and MP2 and the first and second N-channel CMOS transistors MN1 and MN.
2 and an inverter IN1.
And an output signal of the AND circuit 21 described below is generated, and the output of the OR is output from the inverter IN
The first output terminal is applied to the gate of the fifth P-channel CMOS transistor MP5, and is applied to one input of the AND circuit 21 described below.

The AND circuit 21 comprises third and fourth P-channel CMOS transistors MP3 and MP4 and third and fourth N-channel CMOS transistors MN3 and MN.
N4 and an inverter IN2.
2 and the output signal of the above-mentioned OR circuit 20, the logical product of which is output by the inverter I
The output is applied to the gate of the fifth N-channel CMOS transistor MN5 from the output terminal of N2, and is applied to one input of the above-mentioned OR circuit 20. Then, when a signal of a logical value High is applied to the input terminal 22, the drain of the fifth P-channel CMOS transistor MP5 and the fifth N-channel CMOS
Output terminal 2 to which the drain of transistor MN5 is connected
3 outputs a signal of a logical value Low, while a signal of a logical value Low is applied to the input terminal 22, and a signal of a logical value High is output from the output terminal 23. Things.

[0004]

By the way, this CMO
The S-buffer circuit minimizes the so-called through current flowing from the power supply side to the ground through both transistors when the operation states of the fifth P-channel CMOS transistor MP5 and the fifth N-channel CMOS transistor MN5 are switched. It has the characteristic that it is comprised. However, while the through current is reduced, the number of elements is larger than that of a normal buffer circuit which does not consider such suppression of the through current, and the logical sum is increased in order to reduce the through current. Since a so-called through current is generated in the circuit 20 and the AND circuit 21, there is a problem that current consumption is larger than that of a normal buffer circuit.

The present invention has been made in view of the above situation, and provides a CMOS buffer circuit capable of suppressing a so-called through current with a smaller number of elements than a conventional circuit. Another object of the present invention is to provide a CMOS buffer circuit that consumes less current than conventional circuits, can minimize a through current, and can improve the reliability of circuit operation. is there.

[0006]

According to a first aspect of the present invention, there is provided a CMOS buffer circuit, wherein an output stage includes a P-channel CMOS transistor and an N-channel CMOS transistor connected in series between a power supply and a ground. The input signal is applied to the gates of the P-channel CMOS transistor and the N-channel CMOS transistor without being logically converted.

In such a configuration, unlike the related art, the gates of the P-channel CMOS transistor and the N-channel CMOS transistor constituting the output stage are not converted without converting the logic of the input signal, that is, without passing through a so-called operation element. The circuit configuration is simplified by eliminating the need for a so-called arithmetic element as in the prior art.

More specifically, the output stage is a CMOS buffer circuit comprising a P-channel CMOS transistor and an N-channel CMOS transistor connected in series between a power supply and a ground, wherein the output stage comprises A first transfer switch is provided between the gate of the P-channel CMOS transistor and the input terminal.
A first N-channel CMOS transistor for a transfer switch is provided between the gate and the input terminal of the N-channel CMOS transistor constituting the output stage, and the P-channel CMOS transistor is connected in series. The first P channel C
The gate of the MOS transistor is connected to the gate of an N-channel CMOS transistor forming the output stage, and the gate of the first N-channel CMOS transistor is connected to the gate of a P-channel CMOS transistor forming the output stage. On the other hand, a second P-channel CMOS transistor and a second N-channel CMOS transistor are provided in series between a power supply and a ground, and a gate of the second P-channel CMOS transistor is connected to the first P-channel CMOS transistor. The second N-channel CMO is connected to the gate of the N-channel MOS transistor.
The gate of the S transistor is connected to the first P-channel C
The drains of the second P-channel CMOS transistor and the second N-channel CMOS transistor, which are respectively connected and connected to the gate of the MOS transistor, are connected to the gate of the third P-channel CMOS transistor and the third N-channel CMOS transistor. A third P-channel CMOS connected to a gate of a CMOS transistor;
A power supply voltage is applied to a source of the transistor, a drain is connected to a gate of a P-channel transistor constituting the output stage, and a source of the third N-channel CMOS transistor is connected to ground, It is preferable that the drain is configured to be connected to the gate of the N-channel transistor constituting the output stage.

In such a configuration, in particular, a transfer switch for transmitting an input signal to each gate of a P-channel CMOS transistor and an N-channel CMOS transistor constituting an output stage is provided.
The first P-channel CMOS transistor and the first N-channel transistor are provided, and are connected to each other so that the gate voltage of the other output stage transistor is fed back. It is designed to suppress them. That is, the configuration is such that the gate voltages of the CMOS transistors forming the other output stages are fed back to the respective gates of the first P-channel CMOS transistor and the first N-channel CMOS transistor for the transfer switch. Since one of the two CMOS transistors forming the output stage is conductive and the other is non-conductive at the same time, unlike the related art, the period during which the two CMOS transistors forming the output stage are simultaneously conductive is extremely short. , The through current is suppressed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. First, a circuit configuration of a CMOS buffer circuit (hereinafter, referred to as “this circuit”) according to an embodiment of the present invention will be described with reference to FIG. In this circuit, the output stage includes a fourth P-channel CMOS transistor (denoted as “MP4” in FIG. 1) 4 and a fourth N-channel C
A MOS transistor (indicated as “MN4” in FIG. 1) 8 constitutes a so-called push-pull output circuit.
The transistor (hereinafter referred to as “fourth PMOS”) 4
Through a first P-channel CMOS transistor (denoted as “MP1” in FIG. 1) 1, a fourth N-channel CMOS transistor (hereinafter, referred to as “fourth NMOS”) 8 is connected to a first N-channel CMOS transistor. Input signals applied to input terminals 10 are input via transistors (indicated as “MN1” in FIG. 1) 5, respectively.
One of them is configured to be in operation according to the input signal.

That is, the fourth PMOS 4 and the fourth NM
The OS 8 has a drain connected to the output terminal 11, a power supply voltage VDD is applied to a source of the fourth PMOS 4, and a source of the fourth NMOS 8 is connected to the ground, These two MOS4,8
Are connected in series between a power supply and a ground. On the other hand, an input signal to the present circuit is applied to the input terminal 10, and a first P-channel CMOS transistor (hereinafter referred to as a "first PMOS transistor") as a transfer switch element is connected to the input terminal 10. 1) and the drain of a first N-channel CMOS transistor (hereinafter, referred to as “first NMOS”) 5 also serving as a transfer switch element. The drain of the first PMOS 1 is connected to the gate of the fourth PMOS 4 and the first
, And a gate of a second P-channel MOS transistor (described as “MP2” in FIG. 1) 2 to be described later. On the other hand, the first N
The source of the MOS5 is connected to the gate of the fourth NMOS8, and the gate of the first PMOS1 and the second
1 (referred to as “MN2” in FIG. 1). As described above, in the first PMOS 1, the gate voltage of the other transistor paired with the fourth PMOS 4 forming the output stage to which the first PMOS 1 is connected, that is, the gate voltage of the fourth NMOS 8 is fed back to the gate. The first NMOS 5 is connected to the gate voltage of the other transistor paired with the fourth NMOS 8 constituting the output stage to which the first NMOS 5 is connected, that is, the gate voltage of the fourth PMOS 4 is connected to the gate. Connected to provide feedback.

A second P-channel CMOS transistor (hereinafter referred to as “second PMOS”) 2 and a second N-channel CMOS transistor (hereinafter referred to as “second NMOS”) 6 are connected between a power supply and a ground. They are connected in series between them. That is, the drain of the second PMOS 2 and the drain of the second NMOS 6 are connected to each other, and a third P-channel CMOS transistor (described as “MP3” in FIG. 1) 3 and a third N The gate is connected to each gate of a channel CMOS transistor (denoted as “MN3” in FIG. 1) 7. The source of the second PMOS 2 has a power supply voltage V
While the DD is applied, the source of the second NMOS 6 is connected to the ground. The gates of the third P-channel CMOS transistor (hereinafter referred to as “third PMOS”) 3 and the third N-channel CMOS transistor (hereinafter referred to as “third NMOS”) 7 are connected to each other. , The second PMOS 2
And the drain of the second NMOS 6 are connected. The power supply voltage VDD is applied to the source of the third PMOS 3, while the drain of the third PMOS 3 is connected to the fourth PMOS 3.
Is connected to the gate of the PMOS4. The source of the third NMOS 7 is connected to the ground, while the drain is connected to the gate of the fourth NMOS 8.

Next, the operation in this configuration will be described. First, the input signal of the input terminal 10 has the logical value Lo.
In the case of w, first, in describing the operation of each unit, at this time, it is assumed that the drain side of the first PMOS 1 (the side described as “PGATE” in FIG. 1) has a logical value of High. I do. Assuming that the drain side of the first PMOS 1 is in the logic high state, this causes the first NMOS 5 to be in a conductive state, while the second PMOS 4 and the fourth PMOS 4 are both in a non-conductive state. Thereby, the source side of the first NMOS 5 (FIG. 1)
In the figure, the side described as “NGATE”) has the same logical value Low state as that of the input terminal 10, and accordingly, the second
And the fourth NMOSs 6 and 8 become non-conductive,
The first PMOS 1 is turned on. As a result, the drain side of the first PMOS 1 has the same logical value Low as the input terminal 10, and the first NMOS 5 is turned off, while the second and fourth PMOSs 2 and 4 are turned on. It will be in a state. When the second PMOS 2 is turned on, the third PMOS 3 and the third N 3
As a result of the gate voltage of the MOS 7 being substantially equal to the power supply voltage VDD, the third PMOS 3 is turned off and the third N
MOS 7 is rendered conductive. As a result, the first NMO
The source side of S5 is held at a substantially ground potential, the fourth PMOS 4 is turned on, and the fourth NMOS 8 is turned off, so that the output terminal 11 is in the state of the logical value High.

In the above description, first, the first PMOS 1
Has been described assuming that the drain side of the first PMOS 1 has the logical value High. However, when the input terminal 10 has the logical value Low, eventually, the drain side of the first PMOS 1
It can be said that the logic value is stabilized in the low state. If the input terminal 10 is set to the logic low state, the drain of the first PMOS 1 is set to the logic low.
If the operation of each unit is followed by assuming that
OS5 is turned off while the second and fourth PMs are turned off.
OS2 and OS4 become conductive. And the second PMO
When S2 is turned on, the third PMOS 3 is turned off, the third NMOS 7 is turned on, and the first N3 is turned on.
The source side of MOS5 is held at the ground potential. Therefore, the second and fourth NMOSs 6 and 8 are turned off, while the first PMOS 1 is turned on, and the drain side of the first PMOS 1 is set to the same logic value Low state as the input terminal 10. . As a result, the second and fourth PMOSs 2 and 4 become conductive, and as a result, the output terminal 11
Becomes the logical value High state as in the case of the above description.

The source side of the first NMOS 5 has a logical value H
Even in the case where the operation of each unit is pursued assuming that it is high or the logical value is Low, the voltage of each unit is determined basically in the same manner as described above, and eventually, when the input terminal 10 has the logical value Low, , The drain side of the first PMOS 1 has a logical value Lo.
w, the source side of the first NMOS 5 has a logical value of Low,
Each of them is determined, and the output terminal 11 has the logical value High.

Next, the input signal of the input terminal 10 is a logical value H.
The case of “high” will be described. First, at this time,
Assuming that the drain side of the PMOS 1 has a logical value Low, the first NMOS 5 is non-conductive, while the second and fourth PMOSs 2 and 4 are both conductive. When the second PMOS 2 conducts, the third PM 2
OS3 is turned off while the third NMOS 7
Becomes conductive. By the conduction of the third NMOS 7,
Since the source side of the first NMOS 5 is set to a substantially ground potential, the first PMOS 1 is in a conductive state, and the drain side is in the state of the same logical value High as the input terminal 10. As a result, the first NMOS 5 is turned on, and the source side of the first NMOS 5 has the logical value High, and the first P5
MOS1 is turned off. Also, the first NMOS
5, the second and fourth NMOSs 6 and 8 are both turned on when the source side of No. 5 becomes the logic value High, so that the third PMOS 3 is turned on and the third N3 is turned on.
MOS 7 is turned off. And the third PMO
Due to the conduction of S3, the drain side of the first PMOS 1
The second and fourth PMs are held at approximately the power supply voltage VDD.
OS2 and OS4 are turned off. After all, the output terminal 11
Output a logical value Low.

Therefore, if the voltage at the input terminal 10 is at a level corresponding to the logical value Low, the drain side of the first PMOS 1 is at the same voltage level as the input terminal 10 until it rises to a constant voltage. While continuing, the first N
The source side of the MOS 5 is kept at the ground potential. Further, when the input terminal 10 has a logical value of High, the first NMOS is used until the input terminal 10 decreases to a constant voltage.
5 continues to be at the same voltage level as the input terminal 10, while the drain side of the first PMOS 1 is held at the power supply voltage VDD.

For example, the voltage of the input terminal 10 is changed from zero v to 5
v, the voltage on the drain side of the first PMOS 1 becomes the first P
While the MOS transistor 1 rises in the same manner as the input terminal 10 until the MOS transistor becomes non-conductive, the source side of the first NMOS 5 remains at the logical value Low until the first NMOS 5 becomes conductive.
Then, the voltage on the drain side of the first PMOS 1 becomes the second PMOS 1
And when the voltage becomes the cut-off voltage of the fourth PMOS 2 and the fourth PMOS 4 and the voltage at which the first NMOS 5 becomes conductive,
The source side of the NMOS 5 rises to the same voltage as the input terminal 10. When the first NMOS 5 is turned on, the first PMOS 1 is turned off, the second NMOS 6 is turned on, and the third PMOS 3 is turned on. The conduction of the third PMOS 3 causes the first PMOS 1
As a result, the fourth PMOS 4 is turned off and the fourth NMOS 8 is turned on, so that the output terminal 11 outputs the logical value Low. Will be done.

Immediately before the output terminal 11 changes from the logical value High state to the logical value Low state, the voltage on the drain side of the first PMOS 1 becomes the fourth PMOS 1
4 is almost reached, and the fourth PMOS 8 is turned on and the fourth PMOS 4 is turned off at the same time. There is no. Conversely, when the voltage of the input terminal 10 is reduced from 5V to 0V, the voltage on the source side of the first NMOS 5 is reduced in the same manner as the input terminal 10 until the first NMOS 5 is turned off. , The drain side of the first PMOS 1 is connected to the first PMO
It remains at the logic high state until S1 conducts.
Then, when the voltage on the source side of the first NMOS 5 reaches a voltage for conducting the first PMOS 1, the first P5
The voltage on the drain side of the MOS1 becomes the same voltage as that of the input terminal 10, the second PMOS2 is turned on, whereby the third NMOS 7 is turned on, and the source side of the first NMOS 5 drops to the ground potential. . And the fourth PMO
Since the fourth NMOS 8 is turned off while S4 is turned on, the logic value High is output from the output terminal 11.

In this case, the fourth PMOS 4 is turned on at the same time as the fourth NMOS 8
Become non-conductive, the fourth PMOS 4 and the fourth NMO
It can be said that there is almost no so-called through current flowing through S8.
As described above, since there is almost no through current flowing from the power supply side to the ground side, the level of so-called ground noise is extremely low. Therefore, malfunction of the integrated circuit using this circuit is prevented, and at the same time, current consumption is reduced. Will be done

[0021]

As described above, according to the present invention,
Unlike before, input signals do not pass through arithmetic elements,
By applying the voltage to the transistor constituting the output stage, the number of components can be reduced as compared with the conventional case. In particular, an input signal is applied to each of the two CMOS transistors forming the output stage via the transfer switch, and the two transfer switches include a CMOS transistor forming the output stage and a CMOS transistor forming the output stage. By providing a configuration in which the gate voltage of the other CMOS transistor forming a pair is fed back, two CMOs constituting an output stage are provided.
Since it is possible to avoid the timing at which the S-transistors are simultaneously turned on, it is possible to reliably suppress the so-called through current, to reduce the current consumption and to improve the reliability of the circuit operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration example according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional circuit configuration example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st P channel CMOS transistor 2 ... 2nd P channel CMOS transistor 3 ... 3rd P channel CMOS transistor 4 ... 4th P channel CMOS transistor 5 ... 1st N channel CMOS transistor 6 ... 2nd N-channel CMOS transistor 7 ... third N-channel CMOS transistor 8 ... fourth N-channel CMOS transistor 10 ... input terminal 11 ... output terminal

Claims (3)

[Claims] An output stage includes a P-channel CMOS transistor and an N-channel CMOS transistor connected in series between a power supply and a ground, and a gate of each of the P-channel CMOS transistor and the N-channel CMOS transistor is provided. Is a CMOS buffer circuit characterized in that an input signal is applied without being logically converted. 2. P-channel CMOS constituting an output stage
A first transfer switch element for transmitting an input signal to a gate of the transistor; and a second transfer switch element for transmitting an input signal to a gate of an N-channel CMOS transistor forming an output stage. The switching element is the N channel C
A change in the gate voltage of the MOS transistor is fed back to operate, and the second transfer switch element is configured to operate by a change in the gate voltage of the P-channel CMOS transistor being fed back. Item 2. The CMOS buffer circuit according to Item 1. 3. A CM wherein an output stage is constituted by a P-channel CMOS transistor and an N-channel CMOS transistor connected in series between a power supply and a ground.
An OS buffer circuit, wherein a first P-channel CMOS transistor for a transfer switch is provided between an input terminal and a gate of a P-channel CMOS transistor forming the output stage. A first N-channel CMOS transistor for a transfer switch is provided between the gate of the transistor and an input terminal in series, and a gate of the first P-channel CMOS transistor is connected to the output stage. The gate of the first N-channel CMOS transistor is connected to the gate of the first N-channel CMOS transistor.
A second P-channel CMOS is connected between the power supply and the ground while being connected to the gate of the MOS transistor.
A transistor and a second N-channel CMOS transistor are provided in series, and the gate of the second P-channel CMOS transistor is connected to the gate of the first N-channel MOS transistor. Is connected to the gate of the first P-channel CMOS transistor, respectively. The drains of the second P-channel CMOS transistor and the second N-channel CMOS transistor, which are connected to each other, are connected to a third P-channel CMOS transistor. A power supply voltage is applied to a source of the third P-channel CMOS transistor while a drain is connected to a gate of the third N-channel CMOS transistor and a drain of a P-channel transistor constituting the output stage. A source of the third N-channel CMOS transistor is connected to ground, and a drain is connected to a gate of an N-channel transistor constituting the output stage. Buffer circuit.