JPH02254814A - Tri-state output buffer circuit - Google Patents

Abstract

PURPOSE:To constitute a 3-state output buffer circuit of CMOS constitution with a few number of MOS transistors(TRs) by inserting an n-channel MOS TR between a drain and a control terminal of a p-channel MOS TR at a power supply terminal side forming a 2-input NOR gate. CONSTITUTION:Two p-channel MOS TRs 101, 102 and 2 n-channel MOS TRs 103, 104 constitute a 2-input NOR gate. Then when a control signal 02' is at an H level, that is, the output is inhibited, H, L levels are inputted respectively to gates of p-channel and n-channel MOS TRs 106, 107 to turn off the both. When the control signal 02' is at an L level, whether the TR 101 is turned on or the TRs 103, 105 are turned on depends on whether an input signal 01 is at an 11 or an L level automatically. Then either of the TRs 106, 107 is turned on and an output is obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a three-state output buffer circuit.

[Conventional technology]

Figure 3(a) shows the configuration of a conventional CMO33 state buffer circuit, that is, a buffer circuit that outputs input signals in positive or negative phase and has the function of setting the output to a high impedance state (Z) using a control signal. Shown below.

This conventional example has a two-man power NAND gate T2 with an 0MO8 configuration connected to the output terminal of an inverter T1 with input terminals of CMO3il configuration, and a two-man power NOR gate T3 with a CMOS configuration whose inputs are input terminal 01 and control terminal 02. The output of the two-way NAND gate T2 is connected to the gate of the pMOS transistor 106, and the two-way NOR gate T3 is connected to the gate of the nMOS transistor 107. In addition, the pMOS transistor 106 and the nMOS
The drain of transistor 107 is connected to output terminal 0
It becomes 5.

When the potential level of the control terminal is “L I+”, it is a two-man power NAN.
The part of the D gate T2.2 and the manual NOR gate T3 is connected to the signal line 0, which indicates the function of the inverter with respect to the input signal (01).
An inverted signal of the input signal is output to terminals 3 and 04, and an output signal having the same phase as the input signal is obtained at the output terminal 105. Furthermore, when the potential level of the control terminal is °H''', the output of the two-man power NAND gate T2 becomes the "H'" level, the output of the two-man power NOR gate T3 becomes the "L" level, and the output terminal 05 becomes the "H" level, regardless of the input signal. It becomes a high impedance state <2>.

[Problems to be Solved by the Invention] The conventional three-state output buffer circuit described above has a front stage portion consisting of an inverter T1, two manually powered NAND gates T2, and two manually powered NOR gates T3.
If it is made into an i-format, 10 MOS transistors are required in the front stage portion, the circuit configuration becomes complicated, and the area occupied in the layout area becomes large.

[Means to solve the problem]

The three-state output buffer circuit of the present invention has a first p-type buffer circuit whose gate is connected to an input terminal and whose source is connected to a power supply terminal.
M OS transistor, a second pMOS transistor whose gate is connected to the control terminal and whose source is connected to the drain of the first pMOS transistor, whose gate is connected to the input terminal and which connects the drain of the second pMOS transistor and the ground terminal; C consisting of a first nMOS transistor inserted between and a second nMOS transistor whose gate is connected to the control terminal and inserted between the drain of the second pMOS transistor and the ground terminal.
a MOS NOR gate; a third nMOS transistor having a gate connected to the input terminal and inserted between the control terminal and the drain of the first PMOS transistor; and a third nMOS transistor having a gate connected to the drain of the first PMOS transistor. a third pM whose source is connected to the power supply terminal;
an OS transistor, a fourth nMOS transistor having a gate connected to the drain-in of the second pMOS transistor and inserted between the third pMOS transistor and the ground terminal, and a fourth nMOS transistor connected to the drain of the fourth nMOS transistor. It includes an output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a circuit diagram of an embodiment of the present invention, FIG.
b) is a diagram showing the truth value of the operation of the circuit of FIG. 1(a).

2 with the first pMOS transistor 101, the second pMOS transistor 102, the first nMOS h range meta 103, and the second nMOS transistor 104.
An nM OS transistor 1 constitutes a human-powered NOR gate, and its output signal is connected to the ground terminal.
07 gate input.

Moreover, the drain of the first pMOS transistor 101 is
It is connected to the source of the second nMOS transistor 102 and to the gate of a third pMOS transistor 106 whose source is connected to the power supply terminal. Control terminal 02
and the drain of the first pMOS transistor.
A MOS transistor 105 is inserted. The drain of the third pMOS transistor is the output terminal 105
and the drain of the fourth nMOS transistor 107. first nMOS transistor 101,
The input terminal 01 is connected to the gates of the first nMOS transistor 103 and the third nMOS transistor 105, and the input terminal 01 is connected to the gates of the first nMOS transistor 103 and the third nMOS transistor 105.
The gate of the OS transistor 104 and the third nM
The control terminal 02 is connected to the source of the OS transistor 105.
is connected.

Next, the operation of this circuit will be explained. First, when the potential of the control terminal 02 is at the "L" level and the potential at the input terminal 01 is at the "L" level, 101 and 102 are on and 103 is on.
, 104 are turned off, and the "H" level is output to the signal line 04. Also, since signal line 105 is off, signal line 03 is “H”.
Since 106 is turned off and 107 is turned on, the "L'" level is outputted to the output terminal 05.

Next, if the input signal (01) is °“H” level, 101.
Since the signal line 104 is off and the signal line 103 is on, an "L" level is output to the signal line 04. Also, since 105 is turned on, "L" level is output to signal line 03, 106 is turned on, and 107 is turned off, so output terminal 05 is outputted with "H" level.
”Lebel is output.

Next, if the control signal (02) is at °゛H゛H゛ level and the input signal (01) is at “L” level, then 101.104
is on, 102, 103, and 105 are off, so a "H" level is output to signal line 03, a "L" level is output to signal line 04, and 106 and 107 are off, so signal line 05 becomes a high impedance state. . Next, input signal (01
) or “°H” level, 101 and 102 are off, 1
Since 03.104 is turned on, the "L" level is output to the signal line 04. Further, 105 is turned on, and a negative "H" level of the control signal (02) is outputted to the signal line 03, and 106 and 107 are turned off, so that the output terminal 05 is in a high impedance state.

The operation of this embodiment has been described above, but to summarize, when the control signal (02) is "°H" level, that is, the output is prohibited, the gates 106 and 107 are input When the L level is input and both are turned off, and the control signal (02) is "'L" level, that is, output is permitted, 101 is turned on or 103, 105
is turned on or not when the input signal (01) is “H°” is “L”
``The level is automatically determined, and either 106 or 107 is turned on and output is obtained.

Note that in this embodiment, the input signal (01) is
When the “H” level signal (02) is at the “H” level, the signal line 03 has an nM○S transistor 105 compared to the conventional example.
Although the "H" level that is one stage lower is output, there is no problem if the on-resistance of the nMOS transistor 105 is designed to be small.

In the conventional example shown in FIG. 3, ten MOS transistors were required in the front stage portion, but in this embodiment, only five MOS transistors are required.

FIG. 2(a) is a circuit diagram showing a modification of one embodiment;
b) is a diagram showing the truth value of the operation of the circuit of FIG. 2(a).

A fourth nMOS transistor 105 is connected in parallel with the third nMOS transistor 105.
An nMOS transistor 108 is inserted, and an inverted input signal (01) is applied to its gate. Although the number of MOS transistors is increased by three compared to the first embodiment, it is still two fewer than the conventional example.

〔Effect of the invention〕

As explained above, the present invention enables CMOS with fewer MOS transistors by inserting an nMO9 transistor between the drain of the pMOS transistor on the power supply terminal side and the control terminal constituting the two-power NOR gate. '
*It is possible to configure a 3-state output buffer circuit with
This has the effect of reducing the occupied area.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram of an embodiment of the present invention, and FIG. 1(b) is a circuit diagram of an embodiment of the present invention.
) is a diagram showing the truth value of the operation of the circuit in Figure 1 (a), Figure 2
Figure (a) is a circuit diagram of a modification of one embodiment, Figure 2 (b) is a diagram showing the truth value of the operation of Figure 2 (a), Figure 3 (a) is a circuit diagram of a conventional example, and Figure 3 (a) is a circuit diagram of a conventional example. FIG. 3(b) is a diagram showing the truth value of the operation of the circuit of FIG. 3(a). 01...Input terminal, 02...Control terminal, 03,04
...Signal line, 05...Output terminal, 101...First
pMOS transistor, 102... second pMOS
transistor, 103...first nMOS transistor, 104...second nMOS)-transistor, 10
5... Third nMOS transistor, 106... Third pMOS transistor, 107... Fourth nMOS
S transistor, 108... Fourth pMOS transistor, 109... Fifth pMO8 transistor, 11
0...Fifth nMOS transistor, T1...
・Inverter, T2...2-man power NAND gate, T3
...2-person NOR gate.

Claims (1)

[Claims] a first pMOS transistor whose gate is connected to the input terminal and whose source is connected to the power supply terminal; a second pMOS transistor whose gate is connected to the control terminal and whose source is connected to the drain of the first pMOS transistor; a first nM transistor connected to the input terminal and inserted between the drain of the second pMOS transistor and the ground terminal;
C consisting of an OS transistor and a second nMOS transistor whose gate is connected to the control terminal and inserted between the drain of the second pMOS transistor and the ground terminal.
a MOSNOR gate; a third nMOS transistor having a gate connected to the input terminal and inserted between the control terminal and the drain of the first pMOS transistor;
a third pMOS whose gate is connected to the drain of the first pMOS transistor and whose source is connected to the power supply terminal;
a fourth nMOS transistor having a gate connected to the drain-in of the second pMOS transistor and inserted between the third pMOS transistor and a ground terminal; and an output connected to the drain of the fourth nMOS transistor. A three-state output buffer circuit comprising a terminal.