JPS5432258A - Exclusive logical sum circuit - Google Patents

Exclusive logical sum circuit

Info

Publication number
JPS5432258A
JPS5432258A JP9820077A JP9820077A JPS5432258A JP S5432258 A JPS5432258 A JP S5432258A JP 9820077 A JP9820077 A JP 9820077A JP 9820077 A JP9820077 A JP 9820077A JP S5432258 A JPS5432258 A JP S5432258A
Authority
JP
Japan
Prior art keywords
logical sum
exclusive logical
sum circuit
sets
digital signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9820077A
Other languages
Japanese (ja)
Inventor
Koji Hashiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9820077A priority Critical patent/JPS5432258A/en
Publication of JPS5432258A publication Critical patent/JPS5432258A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase the mounting density and operation speed, by constituting the circuit with the NOR element taking input of N sets of digital signals to take exclusive logical sum and inverters inputting the output of N sets of MOS'FET and NOR elements receiving digital signals.
JP9820077A 1977-08-18 1977-08-18 Exclusive logical sum circuit Pending JPS5432258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9820077A JPS5432258A (en) 1977-08-18 1977-08-18 Exclusive logical sum circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9820077A JPS5432258A (en) 1977-08-18 1977-08-18 Exclusive logical sum circuit

Publications (1)

Publication Number Publication Date
JPS5432258A true JPS5432258A (en) 1979-03-09

Family

ID=14213353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9820077A Pending JPS5432258A (en) 1977-08-18 1977-08-18 Exclusive logical sum circuit

Country Status (1)

Country Link
JP (1) JPS5432258A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170312A (en) * 1983-03-15 1984-09-26 Ohbayashigumi Ltd Core construction of fill-type dam

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170312A (en) * 1983-03-15 1984-09-26 Ohbayashigumi Ltd Core construction of fill-type dam
JPH0341605B2 (en) * 1983-03-15 1991-06-24

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