JPS53121532A - 1-bit delay type full adder - Google Patents

1-bit delay type full adder

Info

Publication number
JPS53121532A
JPS53121532A JP3670677A JP3670677A JPS53121532A JP S53121532 A JPS53121532 A JP S53121532A JP 3670677 A JP3670677 A JP 3670677A JP 3670677 A JP3670677 A JP 3670677A JP S53121532 A JPS53121532 A JP S53121532A
Authority
JP
Japan
Prior art keywords
full adder
bit delay
type full
delay type
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3670677A
Other languages
Japanese (ja)
Other versions
JPS601650B2 (en
Inventor
Shuichi Goto
Kazuhide Aoki
Takashi Totoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3670677A priority Critical patent/JPS601650B2/en
Publication of JPS53121532A publication Critical patent/JPS53121532A/en
Publication of JPS601650B2 publication Critical patent/JPS601650B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To secure the 1-bit delay for the full adder output with a reduced number of the element by giving a switch control to the transfer gate at the input part side of the main circuit via the writing clock pulse and to the transfer gate at the output part side via the reading clock pulse respectively.
JP3670677A 1977-03-31 1977-03-31 1-bit delay type full adder Expired JPS601650B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3670677A JPS601650B2 (en) 1977-03-31 1977-03-31 1-bit delay type full adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3670677A JPS601650B2 (en) 1977-03-31 1977-03-31 1-bit delay type full adder

Publications (2)

Publication Number Publication Date
JPS53121532A true JPS53121532A (en) 1978-10-24
JPS601650B2 JPS601650B2 (en) 1985-01-16

Family

ID=12477206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3670677A Expired JPS601650B2 (en) 1977-03-31 1977-03-31 1-bit delay type full adder

Country Status (1)

Country Link
JP (1) JPS601650B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065353A (en) * 1989-03-31 1991-11-12 Hitachi, Ltd. Adder control method and adder control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065353A (en) * 1989-03-31 1991-11-12 Hitachi, Ltd. Adder control method and adder control circuit

Also Published As

Publication number Publication date
JPS601650B2 (en) 1985-01-16

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