JPS56120208A - Delay circuit of variable length - Google Patents

Delay circuit of variable length

Info

Publication number
JPS56120208A
JPS56120208A JP2355680A JP2355680A JPS56120208A JP S56120208 A JPS56120208 A JP S56120208A JP 2355680 A JP2355680 A JP 2355680A JP 2355680 A JP2355680 A JP 2355680A JP S56120208 A JPS56120208 A JP S56120208A
Authority
JP
Japan
Prior art keywords
input
delay
variable length
binary code
extent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2355680A
Other languages
Japanese (ja)
Other versions
JPS6327891B2 (en
Inventor
Akira Kanemasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2355680A priority Critical patent/JPS56120208A/en
Publication of JPS56120208A publication Critical patent/JPS56120208A/en
Publication of JPS6327891B2 publication Critical patent/JPS6327891B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H03H11/265—Time-delay networks with adjustable delay

Landscapes

  • Complex Calculations (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To give a delay simply, to enable a circuit to be used an arrangement conversion circuit and to establish a circuit suitable for one chip circuit integration, by the selective switching of the connection which gives a delay for two inputs and outputs in series with two delay elements, for two delay elements of variable length having the terminal setting extent of delay. CONSTITUTION:Serial data is input to input terminals 1, 2 and binary code signal 13 to set the extent of delay for a delay element 8 of variable length is input to an input terminal 3. The binary code signal 13 is converted at a binary code conversion circuit 12, where a binary code signal 14 to set the extent of delay of a delay element 9 of variable length can be obtained. Further, the data input to the input terminals 1 and 2 is input to two input selection circuits 10, 11, and either one of them is selected and output with the selection signal input from an input terminal 5.
JP2355680A 1980-02-27 1980-02-27 Delay circuit of variable length Granted JPS56120208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2355680A JPS56120208A (en) 1980-02-27 1980-02-27 Delay circuit of variable length

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2355680A JPS56120208A (en) 1980-02-27 1980-02-27 Delay circuit of variable length

Publications (2)

Publication Number Publication Date
JPS56120208A true JPS56120208A (en) 1981-09-21
JPS6327891B2 JPS6327891B2 (en) 1988-06-06

Family

ID=12113771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2355680A Granted JPS56120208A (en) 1980-02-27 1980-02-27 Delay circuit of variable length

Country Status (1)

Country Link
JP (1) JPS56120208A (en)

Also Published As

Publication number Publication date
JPS6327891B2 (en) 1988-06-06

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