JPS56156017A - Pulse generating circuit - Google Patents

Pulse generating circuit

Info

Publication number
JPS56156017A
JPS56156017A JP6039180A JP6039180A JPS56156017A JP S56156017 A JPS56156017 A JP S56156017A JP 6039180 A JP6039180 A JP 6039180A JP 6039180 A JP6039180 A JP 6039180A JP S56156017 A JPS56156017 A JP S56156017A
Authority
JP
Japan
Prior art keywords
generating circuit
pulse generating
signal output
logical circuit
delay signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6039180A
Other languages
Japanese (ja)
Inventor
Osamu Ikeuchi
Toshio Tanahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6039180A priority Critical patent/JPS56156017A/en
Publication of JPS56156017A publication Critical patent/JPS56156017A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits

Landscapes

  • Pulse Circuits (AREA)

Abstract

PURPOSE:To vary the level ratio or period of the generated pulse, by connecting plural delay signal output terminals to a NOT logical circuit. CONSTITUTION:A repetitive pulse having a ration other than 1:1 between a high level and a low level is generated according to the position of connection of two delay signal output terminals which are connected the input terminals 5 and 6 of a NOT logical circuit 1.
JP6039180A 1980-05-06 1980-05-06 Pulse generating circuit Pending JPS56156017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6039180A JPS56156017A (en) 1980-05-06 1980-05-06 Pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6039180A JPS56156017A (en) 1980-05-06 1980-05-06 Pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS56156017A true JPS56156017A (en) 1981-12-02

Family

ID=13140797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6039180A Pending JPS56156017A (en) 1980-05-06 1980-05-06 Pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS56156017A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04361418A (en) * 1991-06-10 1992-12-15 Nec Ic Microcomput Syst Ltd Ring oscillator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320844B1 (en) * 1971-04-12 1978-06-29

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320844B1 (en) * 1971-04-12 1978-06-29

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04361418A (en) * 1991-06-10 1992-12-15 Nec Ic Microcomput Syst Ltd Ring oscillator

Similar Documents

Publication Publication Date Title
EP0339679A3 (en) Bipolar-cmos digital interface circuit
JPS5698060A (en) Receiving circuit
JPS52146534A (en) Input circuit
MY102916A (en) Measurement circuit.
JPS56156017A (en) Pulse generating circuit
JPS6439815A (en) Noise eliminating circuit
JPS53139456A (en) Clock driver circuit
JPS53100745A (en) Logic circuit
JPS5784618A (en) One shot circuit
JPS6422106A (en) Duty ratio control circuit for pulse signal
SU1166286A1 (en) Generator of discrete signals
JPS56137332A (en) Optical not circuit
JPS5315051A (en) Chattering absorbing circuit of contacts
SU496680A2 (en) Pulse-potential diode-transformer valve
JPS51146152A (en) Signal selection circuit
JPS5730412A (en) Voltage comparison circuit
JPS5595155A (en) Operation check system for counter
JPS6448518A (en) Biphase clock generating circuit
JPS5420649A (en) Digital-to-analog converter circuit
JPS57203320A (en) Sequence deciding circuit
JPS5234648A (en) Delay circuit
JPS522154A (en) Waveform shaping circuit
JPS5541502A (en) Sequence controller
JPS56168476A (en) Polarity switching circuit of video signal
JPS53108359A (en) Trigger circuit