JPS57132430A - Superconductive logical circuit - Google Patents

Superconductive logical circuit

Info

Publication number
JPS57132430A
JPS57132430A JP56017681A JP1768181A JPS57132430A JP S57132430 A JPS57132430 A JP S57132430A JP 56017681 A JP56017681 A JP 56017681A JP 1768181 A JP1768181 A JP 1768181A JP S57132430 A JPS57132430 A JP S57132430A
Authority
JP
Japan
Prior art keywords
circuit
terminal
signal
logical circuit
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56017681A
Other languages
Japanese (ja)
Other versions
JPS622732B2 (en
Inventor
Koji Takaragawa
Akira Ishida
Takashi Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56017681A priority Critical patent/JPS57132430A/en
Priority to US06/269,874 priority patent/US4482821A/en
Priority to GB8117187A priority patent/GB2078046B/en
Priority to NLAANVRAGE8102758,A priority patent/NL188441C/en
Priority to CA000379407A priority patent/CA1169498A/en
Priority to FR8111437A priority patent/FR2484173B1/en
Priority to DE3122986A priority patent/DE3122986C2/en
Publication of JPS57132430A publication Critical patent/JPS57132430A/en
Publication of JPS622732B2 publication Critical patent/JPS622732B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • H03K19/1954—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
    • H03K19/1956—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current using an inductorless circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To execute operation with low electric power at a high speed, by combining plural basic circuits constituted of a bridge containing a Josephson junction. CONSTITUTION:Basic circuits U1, U2 are provided with load resistances RL1, RL2, respectively. Also, a terminal T3 of the circuit U1 and a terminal T2 of the circuit U2 are connected to each other, and from terminals T4 of both the circuits, the respective load resistances are grounded. therefore, in a state that input signals IA and IB are inputted to terminals T1, T2 of the circuit U1, and a signal IA+B flows into the terminal T2 of the circuit U2, when a current IT is made to flow to a terminal T1 of the circuit U2, AND I(A+B).T of the exclusive OR signal IA+B and the signal IT is obtained to the terminal T4 of the circuit U2.
JP56017681A 1980-06-10 1981-02-09 Superconductive logical circuit Granted JPS57132430A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP56017681A JPS57132430A (en) 1981-02-09 1981-02-09 Superconductive logical circuit
US06/269,874 US4482821A (en) 1980-06-10 1981-06-03 Superconductive logic circuit
GB8117187A GB2078046B (en) 1980-06-10 1981-06-04 Superconductive logic circuit
NLAANVRAGE8102758,A NL188441C (en) 1980-06-10 1981-06-09 SUPER CONDUCTIVE LOGIC CIRCUIT.
CA000379407A CA1169498A (en) 1980-06-10 1981-06-10 Superconductive logic circuit
FR8111437A FR2484173B1 (en) 1980-06-10 1981-06-10 SUPERCONDUCTIVE LOGIC CIRCUIT
DE3122986A DE3122986C2 (en) 1980-06-10 1981-06-10 Injection current-controlled basic circuit with Josephson elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56017681A JPS57132430A (en) 1981-02-09 1981-02-09 Superconductive logical circuit

Publications (2)

Publication Number Publication Date
JPS57132430A true JPS57132430A (en) 1982-08-16
JPS622732B2 JPS622732B2 (en) 1987-01-21

Family

ID=11950578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56017681A Granted JPS57132430A (en) 1980-06-10 1981-02-09 Superconductive logical circuit

Country Status (1)

Country Link
JP (1) JPS57132430A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01118538U (en) * 1988-02-05 1989-08-10
JPH01119725U (en) * 1988-02-10 1989-08-14
JPH04101438U (en) * 1991-02-07 1992-09-02 株式会社イナツクス resin backed tiles

Also Published As

Publication number Publication date
JPS622732B2 (en) 1987-01-21

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