JPS6458118A - Input and output circuit - Google Patents

Input and output circuit

Info

Publication number
JPS6458118A
JPS6458118A JP62215591A JP21559187A JPS6458118A JP S6458118 A JPS6458118 A JP S6458118A JP 62215591 A JP62215591 A JP 62215591A JP 21559187 A JP21559187 A JP 21559187A JP S6458118 A JPS6458118 A JP S6458118A
Authority
JP
Japan
Prior art keywords
terminal
input
level
terminals
transfer gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62215591A
Other languages
Japanese (ja)
Inventor
Shinichi Koazechi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62215591A priority Critical patent/JPS6458118A/en
Publication of JPS6458118A publication Critical patent/JPS6458118A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To handle analog and digital signals by one device by providing a line passable an analog signal and using logic signals at two terminals so as to switch the path for the analog and digital signals. CONSTITUTION:In giving 'H' level to terminals 1, 2, a terminal 3 reaches a high impedance, a 4th transfer gate 19 is conductive and the analog input/output mode is attained between terminals 3 and 4. Moreover, a 2nd transfer gate 17 is conductive and the input of a 4th inverter 8 is fixed to a GND level. In giving an 'L' level to the terminal 1 and 'H' level to the terminal 2, the terminal 3 reaches a high impedance, a 1st transfer gate 16 and a 3rd transfer gate 18 are conductive to form the digital mode using the terminal 3 as the input and the terminal 4 as the output. In giving an 'L' level to the terminal 2, the digital mode is attained, where the terminals 3, 4 are used as the inverted outputs and the terminal 1 is used as the input.
JP62215591A 1987-08-28 1987-08-28 Input and output circuit Pending JPS6458118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62215591A JPS6458118A (en) 1987-08-28 1987-08-28 Input and output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62215591A JPS6458118A (en) 1987-08-28 1987-08-28 Input and output circuit

Publications (1)

Publication Number Publication Date
JPS6458118A true JPS6458118A (en) 1989-03-06

Family

ID=16674964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62215591A Pending JPS6458118A (en) 1987-08-28 1987-08-28 Input and output circuit

Country Status (1)

Country Link
JP (1) JPS6458118A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152962A (en) * 1991-11-26 1993-06-18 Mitsubishi Electric Corp Semiconductor device
JPH06244371A (en) * 1992-10-05 1994-09-02 Matsushita Electric Ind Co Ltd Semiconductor device
US6353296B1 (en) 1999-10-15 2002-03-05 Motorola, Inc. Electronic driver circuit with multiplexer for alternatively driving a load or a bus line, and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152962A (en) * 1991-11-26 1993-06-18 Mitsubishi Electric Corp Semiconductor device
JPH06244371A (en) * 1992-10-05 1994-09-02 Matsushita Electric Ind Co Ltd Semiconductor device
US6353296B1 (en) 1999-10-15 2002-03-05 Motorola, Inc. Electronic driver circuit with multiplexer for alternatively driving a load or a bus line, and method

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