JPS54111269A - Driver using logical integrated circuit - Google Patents
Driver using logical integrated circuitInfo
- Publication number
- JPS54111269A JPS54111269A JP1887778A JP1887778A JPS54111269A JP S54111269 A JPS54111269 A JP S54111269A JP 1887778 A JP1887778 A JP 1887778A JP 1887778 A JP1887778 A JP 1887778A JP S54111269 A JPS54111269 A JP S54111269A
- Authority
- JP
- Japan
- Prior art keywords
- power source
- terminal
- input
- integrated circuit
- logical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To obtain the zero-crossing signal in a simple constitution by branching logical input signals and inputting one to the input side of the logical integrated circuit connected to a positive power source and inputting the other to the input side of the logical integrated circuit connected to a negative power source through a level shift circuit and composing output sides through the resistance. CONSTITUTION:The positive power source is applied to power source terminal 303 and ground terminal 304 of one IC element 30 consisting of I<2>L IC, and the negative power source is applied to ground terminal 308 and power source terminal 309 of the other IC element 31. Next, terminals 304 and 308 of these elements are connected, and the logical input signal from input terminal 301 is supplied to the input side of element 30. At the same time, the input signal is branched and is supplied to the input side of element 31 through diode 305. Then, bias resistance 306 is connected to diode 305 to constitute the level shift circuit, and resistance 306 is connected to terminal 309. In this constitution, output terminals 302 and 307 of these elements are connected to output terminal 310 through resistances 311 and 312 respectively, thus obtaining the composite signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1887778A JPS54111269A (en) | 1978-02-20 | 1978-02-20 | Driver using logical integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1887778A JPS54111269A (en) | 1978-02-20 | 1978-02-20 | Driver using logical integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54111269A true JPS54111269A (en) | 1979-08-31 |
Family
ID=11983774
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1887778A Pending JPS54111269A (en) | 1978-02-20 | 1978-02-20 | Driver using logical integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54111269A (en) |
-
1978
- 1978-02-20 JP JP1887778A patent/JPS54111269A/en active Pending
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