JPS6472619A - Tri-state output circuit - Google Patents

Tri-state output circuit

Info

Publication number
JPS6472619A
JPS6472619A JP62228259A JP22825987A JPS6472619A JP S6472619 A JPS6472619 A JP S6472619A JP 62228259 A JP62228259 A JP 62228259A JP 22825987 A JP22825987 A JP 22825987A JP S6472619 A JPS6472619 A JP S6472619A
Authority
JP
Japan
Prior art keywords
output
tri
state
signal
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62228259A
Other languages
Japanese (ja)
Inventor
Mitsuru Fujishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62228259A priority Critical patent/JPS6472619A/en
Publication of JPS6472619A publication Critical patent/JPS6472619A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To independently set an optional output to a high or a low level without increasing number of terminals, by utilizing positively an input protection diode and an output parasitic diode. CONSTITUTION:A control circuit changing the output of the tri-state value at a high impedance state is constituted by using input protection diodes 5, 6 of a tri-state output circuit and output parasitic diodes 7, 8. Then a signal different from the conventional logic level is applied to the input of the tri-state output circuit at the high impedance state to extract the output of the tri-state output circuit as a binary level signal in response to the signal. Thus, even when the output is in the high impedance state, the output level is set independently to a high or a low level by applying the signal of a logic level different from the conventional logic level to the input.
JP62228259A 1987-09-14 1987-09-14 Tri-state output circuit Pending JPS6472619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62228259A JPS6472619A (en) 1987-09-14 1987-09-14 Tri-state output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62228259A JPS6472619A (en) 1987-09-14 1987-09-14 Tri-state output circuit

Publications (1)

Publication Number Publication Date
JPS6472619A true JPS6472619A (en) 1989-03-17

Family

ID=16873667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62228259A Pending JPS6472619A (en) 1987-09-14 1987-09-14 Tri-state output circuit

Country Status (1)

Country Link
JP (1) JPS6472619A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014014140A (en) * 2013-09-02 2014-01-23 Agere Systems Inc High-voltage-tolerant input/output interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014014140A (en) * 2013-09-02 2014-01-23 Agere Systems Inc High-voltage-tolerant input/output interface circuit

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