JPS6316047B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to flip-flop circuits.

The conventionally widely known flip-flop circuit with current switching type set/reset requires a large number of elements and a circuit that generates a delicate voltage, and therefore consumes a large amount of power. In a semiconductor integrated circuit, it is preferable that the number of elements and power consumption be as small as possible.

FIG. 1 shows a conventional reset flip-flop circuit diagram.

The operation of the circuit shown in FIG. 1A will be explained using FIG. 1B. At the timing of _T1 , the input In3 is at a low potential, the input In1 is at a high potential, and the input In2 is at a low potential, so the transistors 15 and 21 become conductive and Out5 becomes a high potential. At the timing of T ₂ , the input In2 is at a high potential, so the transistor 2
1 is in a cut-off state, and transistor 20 is in a conductive state, but since the output Out5 was at a high potential in the previous state, transistors 16 and 14 are in a conductive state, and the current flows through resistor 9 and transistors 14 and 20, resulting in a constant current. Since it flows through the source I1, the output Out5 is at a high potential as in the previous state. At the timing of _T3 , the input In3 is at a high potential, so the transistors 24 and 20 become conductive, and the output Out5 becomes a low potential. Input In at timing T ₄
3 is at a low potential, but the input In2 is at a high potential, so the transistor 20 is in a conductive state, and since the output Out6 was at a high potential in the previous state, the transistors 17 and 13 are in a conductive state, and the current flows to the resistor 8 transistor 13, Since the current flows through the constant current source I1 through the constant current source I1, the output Out5 becomes a low potential as in the previous state. At the timing of _T5 , since the state is the same as the timing of _T1 , the output Out5 becomes a high potential. Since the input In3 is at a high potential at the timing _T6 , the output Out5 is at a constant potential as at the timing _T3 . At the timing of T ₇ , input In3,
Since In2 is at a low potential, the transistor 20 is cut off and the transistor 21 is turned on, so the input
Since In1 is at a high potential, the transistor 12 is in a cut-off state, and the transistor 15 is in a conductive state, and the current flows through the constant current source _I1 through the resistor 9 and transistors 15 and 21, so that the output Out5 is at a high potential. In the above explanation, if data is connected to In1, a clock is connected to In2, and a reset signal is connected to In3, the flip-flop becomes a flip-flop with reset whose state is reset when a reset signal is applied while the clock is holding data. function can be obtained.

However, when operating the clock or reset signal of such a conventional flip-flop with an inverting input, it is necessary to connect an inverter at the front stage.Generally, an inverter consists of at least one resistor, two transistors, and one current source. Since a power source is required, many elements and current sources are required.

An object of the present invention is to provide a flip-flop circuit with a reduced number of elements and power consumption.

In the flip-flop circuit according to the present invention, the collector of the first transistor is connected to the common emitter of the differential transistors to be connected to the constant current source of the transistor pair, and the constant current source is connected to the emitter of the transistor. is connected to a constant voltage source. a second transistor that operates differentially with the first transistor;
, and the collector of the second transistor is connected to the resistor connected to the collector of the top transistor. If the input voltage applied to the base of the second transistor is lower than the potential of the constant voltage source, the input transistor is in a cut-off state and the first transistor connected to the constant voltage source is in a conductive state, so that the basic flip-flop The circuit operates, but if the input voltage is higher than the constant voltage source, the first transistor connected to the constant voltage source is cut off, and the second transistor connected to the input signal is conductive. Therefore, the current of the constant current source flows through the resistor connected to the collector of the uppermost transistor regardless of other input potentials, and the output terminal connected to the resistor becomes a low potential, thereby obtaining a set or reset state.

Further, when operating the set or reset signal with an inverted input, it is sufficient to simply switch the base inputs of the first transistor and the second transistor.

Next, the present invention will be explained with reference to the drawings.

FIG. 2 shows a reset flip-flop circuit diagram of a preferred embodiment of the present invention. The emitters of transistors 20 and 21 are connected to the collector of transistor 25. A constant voltage power supply Vref4 is connected to the base of the transistor 25. The emitter of the input transistor 24 and the constant current source I1 are connected to the emitter of the transistor 25. transistor 2
Connect the base of No. 4 to In3, which becomes the reset input. The collector of the transistor 24 is connected to the output terminal Out5. When the potential of In3 is lower than the constant voltage power supply Vref4, the potential of Out5 is influenced by In1 and In2 and the flip-flop circuit operates, but when the potential of In3 is higher than Vref4, the transistor 25 is operated. is cut off, transistor 24 is turned on, and Out5 is turned off.
A low potential is obtained, resulting in a reset state.

The operation of the circuit shown in FIG. 2 will be explained using FIG. 3. Since In3 is at a low potential at the timing of _T1 , the positive output terminal Out5 is at a low potential because it is determined by the states of In1 and In2. Since In3 becomes a high potential at the timing of _T2 , Out5 becomes a low potential and maintains the previous state regardless of In1 and In2. At the timing of _T3 , In3 becomes a low potential, but since Out5 was at a low potential in the previous state, the holding transistor 16 is cut off, 17 becomes conductive, and the transistor 13 becomes conductive, so the current flows through the resistance. 8. Since the current flows to the constant current source through transistor 13, transistor 21, and transistor 25, Out5 becomes a low potential and maintains the previous state. At the timing of T ₅ , Out5 is In
However, since In3 becomes high potential at the timing of _T6 , the transistor 24 becomes conductive, and the current flows through the resistor 8 and the transistor 24 to the constant current source, so that Out5 becomes high again. At the timing of _T7 when the potential becomes low, In3 becomes a low potential, so the transistor 25 becomes conductive. Since In2 is at a high potential, the transistor 20 becomes conductive. Since In1 is at a high potential, the transistor 15 becomes conductive, and the current flows to the constant current source through resistor 9, transistor 15, transistor 20, and transistor 25, so Out
5 is a high potential.

FIG. 4 shows a master/slave/flip-flop circuit diagram with reset according to another embodiment of the present invention. A transistor 25 is connected to the emitters of transistors 20 and 21, and a collector of a transistor 27 is connected to the emitters of transistors 22 and 23. A constant voltage power supply Vref4 is connected to the bases of the transistors 25 and 27. The emitter of the transistor 25 is connected to the emitter of the input transistor 24 and the collector of the constant current source generating transistor 28. The emitter of transistor 27 is connected to the emitter of transistor 26 and the collector of constant current source generating transistor 29. The bases of transistors 24 and 26 serve as reset inputs.
Connect to In3. The collector of the transistor 24 is connected to the terminal 32, and the collector of the transistor 26 is connected to the positive output terminal Out5. When the potential of In3 is lower than the constant voltage power supply Vref4, the potential of Out5 is influenced by In1 and In2, and the master-slave flip-flop circuit operates, but the potential of In3 is lower than the constant voltage power supply Vref4. When the potential is high, transistors 25 and 27 are both cut off, transistors 24 and 26 are both conductive, and the terminals 32 and Out5 are reset because a low potential is obtained.

The operation of the circuit shown in FIG. 4 will be explained using FIG. At the timing of _T1 , since In3 is at a low potential, a low potential appears at Out5 in accordance with the operation of a master-slave flip-flop. At the timing of T ₂ , In3 becomes high potential, so the transistor 24
Since terminals 32 and 26 become conductive, the potentials of In1 and In2 are ignored, and terminals 32 and Out5 become low potentials, so Out5 maintains its previous state. At the timing of T ₃ , In3 becomes low potential, but In1 and In
Since Out5 was at a low potential in the previous state, the transistor 18 is cut off and the transistor 17 is turned on, but for this reason, the current flows through the resistor 10, transistors 17, 23, and 2.
Since the current flows through 7 to the constant current source, Out5 becomes a low potential and maintains the previous state. At the timing of T ₅
Since In1 and In2 have a high potential, Out5 has a high potential, but since In3 has a high potential at the timing of T ₆ , it is the same as the state at the timing of T ₂ .
Out5 becomes a low potential. At the timing of T ₇
In3 is at a low potential In1 and In2 are at a high potential, but in the previous state, node 32 is at a low potential and node 33 is at a high potential.
Transistor 16 is in a conductive state, transistor 19 is in a conductive state
is cut off and Out5 becomes a low potential.

FIG. 6 shows another embodiment of the invention. This embodiment is an example in which input transistors 34 and 35 whose collectors are also connected to the negative output side are added to the previous embodiment to provide both set and reset functions. In
The circuit operation for In 4 is exactly the same as that for In 3 described above, except that the negative output goes to low potential only when the input goes to high potential, and therefore operates as a flip-flop with set/reset. A circuit is obtained. FIG. 7 shows its operating waveforms. As described above, according to the present invention, even when clock and reset signals are introduced as inverted inputs, stable reset and set functions can be realized with a small number of elements and without requiring delicate setting of resistance values.

[Brief explanation of the drawing]

FIG. 1 is a conventional circuit diagram, FIG. 2 is a circuit diagram of a preferred embodiment of the present invention, FIG. 3 is a voltage waveform diagram of each part to explain the operation of FIG. 2, and FIGS. 4 and 6. are circuit diagrams showing embodiments of the present invention, and FIGS. 5 and 7 are voltage waveform diagrams of various parts for explaining the circuits of FIGS. 4 and 6, respectively. 8, 9, 10, 11...Resistance for output voltage generation,
12, 13, 14, 15, 16, 17, 18, 1
9, 20, 21, 22, 23, 24, 25, 2
6, 27, 28, 29...transistor, 30,
31... Resistor for constant current source, 32... Master side negative output terminal, 33... Master side positive output terminal,
In1...terminal for data input, In2...terminal for clock input, In3...terminal for reset input, In4...
...Set input terminal, Out5...affirmative output terminal,
Out6...Negation output terminal, I1, I2, I3, I
4, I5... Indicates a constant current source.

Claims (1)

[Claims] 1 In a current-switching flip-flop circuit using vertical logic, a first transistor is connected to the common emitter of a transistor pair that switches the current path between a data writing transistor set and a data holding transistor set in response to a clock input. at least one second transistor that operates differentially with the first transistor; the emitters of the first and second transistors are commonly connected to a constant current source; A set or reset signal is applied to the base of one of the first or second transistors, and a constant voltage power supply is applied to the base of the other transistor to cause differential operation, and the collector of the second transistor generates an output voltage. A flip-flop circuit characterized by being connected to a resistor.