JPS6347368B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current switching type flip-flop circuit using vertical logic.

FIG. 1 shows a conventionally widely known flip-flop circuit with a current switching type set. The operation of the circuit shown in FIG. 1 will be explained using the waveform diagram shown in FIG. At timing _T0 , the clock input terminal In3 is at a high potential, so transistors 3 and 14 are in a conductive state, and the transistor 15 is in a cut-off state.Since the set input terminal In2 is at a low potential, transistors 4, 5, and 12 are cut off. Since the transistor 13 is in a conductive state and the data input terminal In1 is at a high potential, the transistor 7 is in a conductive state and the transistor ₁₀ is in a cut-off state. , 14, the positive output terminal Out1 is a high potential, the negative output terminal
Out1 is at low potential. Next, at timing _T1 , when the data input terminal In1 becomes a low potential, the transistor 7 is cut off, the transistor 10 is turned on, and the current that had been flowing through the resistor 1 stops flowing, and now the resistor 2, the transistor 10, 1
The current of the constant current source I1 flows through 3 and 14, the positive output terminal Out1 is at a low potential, and the negative output terminal 1 is at a low potential.
becomes a high potential.

When the clock input terminal In3 becomes low potential at timing _T2 , transistors 3 and 14 become cut off, and since the negative output terminal 1 was at a high potential until now, transistor 8 becomes cut off and transistors 9 and 15 become conductive. , the current of constant current source I1 flows through resistor 2 and transistors 9 and 15, and outputs positive output terminal Out1 and negative output terminal 1.
is the same as the previous state, the positive output terminal Out1 is at a low potential, and the negative output terminal 1 is at a high potential.

When the set input terminal In2 becomes high potential at timing _T3 , transistors 4, 5, 6, 1
2 and 14 are in a conductive state, transistors 11, 13,
15 is in a cut-off state, current from constant current source I1 flows through resistor 1 and transistors 6, 12, and 14, positive output terminal Out1 is at a high potential, and negative output terminal is at a high potential.
Out1 becomes a low potential.

When the set input terminal In2 becomes a low potential at timing _T4 , the clock input terminal In3 is at a low potential, so the transistors 3 and 14 are cut off and the transistor 15 becomes conductive. Therefore, the transistor 8 is in a conductive state and the transistor 9 is in a cut-off state, the current of the constant current source I1 flows through the resistor 1 and the transistors 8 and 15, the positive output terminal Out1 is at a high potential, and the negative output terminal 1 is at a constant potential. Become.

Therefore, data is placed on terminal In1, and set on terminal In2.
By connecting each clock signal to terminal In3, the function of a flip-flop with set can be obtained. However, conventional flip-flop circuits require a large number of current sources, resulting in disadvantages of power consumption and large number of elements.

An object of the present invention is to provide a flip-flop circuit with low power consumption and low number of elements.

In the flip-flop circuit according to the present invention, the emitter of a first transistor is connected to the common emitter of a transistor set for data writing, and the emitter of a second transistor is connected to the common emitter of a transistor set for data retention. The bases of the first and second transistors are connected in common, the collectors are also connected in common, a set signal is given to the bases, and the collectors are connected to the complementary side resistor that generates the output voltage, thereby generating the set signal. When the potential is high, current flows through the complementary side resistor and through this first or second transistor, so the flip occurs regardless of whether the clock is in the data retention or data write state.
The flop can obtain the function of a set flip-flop in which the state is set.

Next, the present invention will be explained using the drawings.

FIG. 3 shows a circuit diagram showing a preferred embodiment of the invention. Transistors 7 and 1 for data writing
The emitter of the first transistor 4 is connected to the common emitter of the transistor 0, and the data holding transistor 8,
By connecting the emitter of the second transistor 5 to the common emitter of transistor 9 and applying a set signal to the bases of the first and second transistors 4 and 5, the collectors are connected to the resistor 1 on the complementary side. Therefore, when the clock signal In3 is at a high potential, the transistor 12 is in a conductive state and the transistor 13 is in a cut-off state, and when the set input terminal In2 is at a high potential, the transistor 4 is always at a high potential or a low potential at the data input terminal In1. Since the transistor 10 is in the conductive state and the transistor 10 is in the cutoff state, the terminal Out1 becomes a high potential and the terminal 1 becomes a low potential.
Furthermore, when the terminal In3 is at a low potential, the transistor 12 is cut off and the transistor 13 is turned on.
In the previous state, when terminal Out1 is at a high potential, transistor 8 is in a conductive state, and transistor 9 is in a cut-off state, transistor 5 is also in a conductive state, and the terminal
Out1 is at a high potential and terminal 1 is at a low potential.In the previous state, Out1 was at a low potential and transistor 8
When is in the cutoff state and transistor 9 is in the conduction state,
First, transistor 5 begins to conduct and current begins to flow through resistor 1. Next, the base potential of transistor 9 becomes low and transistor 9 goes to the cut-off state. Therefore, transistor 8 goes to conduction state, and then transistor 9 becomes completely conductive. When the transistors 5 and 7 are in the cut-off state and conductive, Out1 becomes a high potential and Out1 becomes a low potential.

As described above, according to the present invention, it is possible to obtain a set flip-flop circuit with low power consumption and a small number of elements.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a waveform diagram showing the operation of FIG. 1, and FIG. 3 is a circuit diagram showing a preferred embodiment of the present invention. 1, 2...Resistor, 3-15...Transistor,
I1, I ₂ , I ₃ ... Constant current source, In1 ... Data input terminal, In2 ... Set input terminal, In3 ... Clock input terminal, Out1 ... Positive output terminal, 1 ...
...Negation output terminal.

Claims (1)

[Claims] 1. Connect the emitter of the first transistor to the common emitter of the transistor set for data writing, connect the emitter of the second transistor to the common emitter of the transistor set for data retention, and
and a second transistor whose bases are connected in common, and whose collectors are also connected in common, a set signal is applied to the bases, and the collectors are connected to a complementary side resistor that generates an output voltage.・Flop circuit.