JPH0234211B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit, particularly a logic circuit having a latch function.
Regarding TTL (Transistor Transistor Logic) circuits.

FIG. 3 is a logic block diagram showing an example of a TTL circuit with a latch function. This logic circuit is called an R-latch circuit. As shown in Figure 3a, this circuit consists of two NAND gates, the output of one gate is the input of the other gate, and the output is from the output of the gate to which input terminal S is connected. I'm taking Q.

Further, FIG. 3b is a timing chart showing the operation of the above circuit. As is clear from this figure, when a negative pulse is input to the input terminal, this circuit outputs an L level signal from the output terminal Q,
While an H level signal is input to the input terminal, the output Q is held, and when a negative pulse is input to the input terminal, an H level signal is output from the output terminal Q, and the output Q is held at the input terminal. This circuit operates by holding its output Q while an H level signal is input.

FIG. 1 is a diagram showing a conventional TTL circuit having a latch function for realizing the logic shown in FIG. 3.

A signal is input to the first input transistor _T1 , and a signal is input to the second input transistor _T2 .

A first phase-dividing transistor T ₃ is connected to _the transistor T 1 and the emitter of T ₃ is connected to the base of the output transistor T ₆ .

Transistors T ₄ , T ₅ and resistor R ₃ constitute an off-buffer circuit.

Further, a so-called active pull-down circuit is provided between the base of the transistor T ₆ and the ground, which is composed of resistors R ₁ and R ₂ and a transistor T ₇ and is used to discharge the base charge of the transistor T ₆ .

A second phase splitting transistor _T8 is connected to the second input transistor _T2 , and a transistor _T9 is connected to the emitter of _T8 . In this circuit, an output signal Q is obtained from the collector of the output transistor _T6 in response to an input signal.

The operation of this circuit will be explained below.

In the section of Fig. 3b, that is, =1 (high level), =1 (high level), the output Q is 1
(high level).

Next, when in the interval, that is, input signal = 0 (low level), = 1 (high level), = 1
The transistor _T1 is turned off, and the base current of the transistor _T3 is supplied through the shot barrier diode between the base and collector of _T1 .
_T3 is turned on.

A portion of the current from transistor T ₃ flows through resistors R ₁ , R ₂ and transistor T ₇ to ground, and the rest becomes the base current of transistor T ₆ , turning _it on.

Transistor with shotgun barrier diode
When T ₆ is on, the voltage between its collector and emitter is V _CE 0.4 (V), so a low-level voltage appears at the output terminal Q, which is the output voltage V _O = V _{CE (T6)} 0.4 (V). .

Voltage at this point V _A =V _CE(T3) +V _BE(T6) 0.4+
0.8=1.2 (V).

Therefore, only a voltage of V _A −V _O 0.8 (V) is applied between the base of transistor T ₄ and the emitter of T ₅ ,
Substantially no current flows through T ₄ and T ₅ .

On the other hand, when =0, the transistor T ₂ is on and T ₈ and T ₉ are off.

Next, in the interval of , that is, =1 (high level), =1 (high level), _T2 is turned off. Since the potential at the point is approximately 1.2 (V), the current flowing through the resistor _R6 becomes the collector current of the transistor _T3 through the diode _D1 .

Therefore, no current flows through the transistors T ₈ and T ₉ and they remain off.

The potential at this point is V _B =V _A +V _{F (D1)} 1.6 (V). Note that V _{F (D1)} is the forward voltage of the diode _D1 . Since the transistors T ₃ and T ₆ remain on, the output does not change and remains at a low level.

Next, in the interval of , that is, = 1 (high level), = 0 (low level), the transistor
T ₁ is turned on, the base current of T ₃ is no longer supplied, and T ₃ is turned off. As transistor T ₃ turns off, the current flowing through resistor R ₄ decreases, causing the potential at the point to rise, eventually reaching V _A Vcc.

On the other hand, when transistor T ₃ turns off, transistor T ₆ also turns off, and when the potential at the point is pulled up by R ₄ and the potential difference between the point and the output terminal opens by 1.6 (V) or more, transistors T ₄ and T ₅ turn off. turns on,
Raise output Q to high level.

Finally, the output voltage V _O = V _A − (V _BEC(T4) + V _BE(T5) )
=Vcc-1.6=3.4 (V).

Resistors R ₁ and R ₂ and transistor T ₇ constitute a so-called active pull-down circuit for drawing out the base charge of transistor T ₆ to speed up the transition to the off state.

Next, in the interval of V, that is, = 1 (high level), = 1 (high level), the transistor
When _T1 is turned off, the current flowing through resistor _R5 flows through the shot barrier diode between the base and collector of _T1 .

At this time, since transistor T ₈ is on, this current flows to T ₈ and T ₉ .

Therefore, the potential at the point V _C = V _CE (T ₈ ) + V _BE (T ₉ )
1.2 (V), transistors T ₃ and T ₆ cannot be turned on, and the output Q remains at high level.

As explained above, this circuit functions to hold the immediately previous state of the output Q when =1 (high level) and =1 (high level). This kind of conventional circuit obtains only the output Q, that is, no output is necessary, and has a configuration in which the collector and base of the transistor _T9 are connected, and has the disadvantage of having a large number of elements from the point of view of circuit function. .

SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional drawbacks and provide a logic circuit that has a small number of elements and can therefore be highly integrated.

Such an object of the invention is the transistor _T8
Focusing on the fact that and _T7 operate in phase, the second
This is achieved by providing a discharging transistor whose base is connected to the emitter of the phase splitting transistor and whose collector is connected to the base of the output transistor via a diode.

An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same symbols as in FIG. 1 indicate the same things.

As is clear from the figure, in the present invention, the transistor
Provided T ₁₀ and diode D ₂ . That is, a transistor is connected to the emitter of the second phase-dividing transistor _T8.
The base of T ₁₀ is connected and the collector of T ₁₀ is
Diode D ₂ is connected to output transistor T ₆
connected to the base of.

The operation of this circuit will be explained below.

In the section of Fig. 3b, that is, =1 (high level), =1 (high level), the output Q is 1
(high level).

Next, in the interval , that is, when =0 and =1, the transistor T ₁ is off and T ₃ and T ₆ are on, so the output voltage V _O =V _CE(T6) becomes a low level of 0.4 (V). Become.

Also, since transistor T ₂ is on, T ₈ , T ₁₀
is turned off.

Next, in the interval of , that is, = 1 (high level), = 1 (high level), the transistor
T ₂ is turned off.

On the other hand, since the transistor _T3 is on, the current flowing through the resistor _R6 becomes the collector current of _T3 via the diode _D1 . This allows the transistor
T ₈ and T ₁₀ remain off. Also transistor
Since T ₃ and T ₆ are on, the output potential does not change.

Next, in the interval of , that is, = 1 (high level), = 0 (low level), the transistor
T ₁ is on, T ₃ and T ₆ are off, and the output Q becomes high level.

Also, since transistor T ₃ is turned off, the current flowing through R ₆ passes through the shot barrier diode between the base and collector of T ₂ and passes through transistors T ₈ and
Turn on T ₁₀ .

As a result, a discharge path for the base charge of T ₆ is formed by T ₁₀ and D ₂ .

Next, in the interval of V, that is, = 1 (high level), = 1 (high level), the transistor
_T1 is turned off, and the current flowing through resistor _R5 flows through the shot barrier diode between the base and collector of _T1 .

Since T ₈ is on, this current flows to ground via T ₈ and T ₁₀ , and T ₃ and T ₆ remain off. Therefore, the output Q remains at high level.

Also, when =0, =0, the transistors T ₁ ,
T ₂ is turned on, T ₃ , T ₆ , T ₂ , and T ₈ are turned off, and the output Q becomes high level.

Note that the diode _D2 is provided to speed up the off-transient of _T3 . That is, T ₁₀
Since the transistors T ₉ and T ₇ of the conventional circuit are shared, one transistor is not required.
Moreover, an active pull-down circuit that requires resistors R ₁ and R ₂ is also unnecessary. Therefore, the number of elements is reduced.

Furthermore, since T ₁₀ and D ₂ can be formed in the same isolation, together with the reduction in the number of transistors mentioned above, the area occupied on the circuit chip can be reduced.

As explained above, according to the present invention, the number of elements can be reduced and high integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a logic block diagram and timing chart of a TTL circuit having a latch function. T ₁ : first input transistor, T ₂ : second input transistor, T ₃ : first phase split transistor, T ₄ : second phase split transistor, T ₆ :
Output transistor, T ₁₀ : Discharge transistor,
_D2 : Diode.

Claims (1)

[Claims] 1. An emitter connected to a first input terminal;
a first input transistor T1 of one conductivity type and Schottky clamp type having a base connected to a first power supply Vcc via a first resistor R5; and a first input transistor T1 of the Schottky clamp type connected to the collector of the first input transistor T1 a first phase splitting transistor T3 of one conductivity type having a base and a collector connected to the first power supply Vcc via a second resistor R4; an output transistor T6 of one conductivity type, having a base connected to the output terminal Q, a collector connected to the output terminal Q, and an emitter connected to the second power supply GND;
and the emitter connected to the second input terminal, the first power supply Vcc via a third resistor R6, and the first phase splitting transistor T3 via the anode and cathode of the first diode D1. a second input transistor T2 of one conductivity type, shot-clamp type, having a base connected to the collector of the transistor T2;
and a second phase splitting transistor T of one conductivity type having a base connected to the collector of the second input transistor T2 and a collector connected to the base of the first phase splitting transistor T3.
8, further comprising: connecting the second power source to the emitter of the second phase splitting transistor T8 and via a fourth resistor R4;
a base connected to GND, and a collector connected to the base of the output transistor T6 via the cathode/anode of the second diode D2;
A logic circuit comprising a discharge transistor T10 of one conductivity type connected to the second power supply GND.