JPH0413853Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar saturated logic circuit with a turn-off time that is slower than a turn-on time.

Logic circuits that have been widely used in the past include diode-transistor logic (hereinafter abbreviated as DTL) and transistor-transistor logic (hereinafter abbreviated as TTL).

Figure 1 shows a NAND circuit, which is the basic circuit of TTL.

The propagation delay time of this type of circuit is the turn-on time when the output transistor Q3 is turned on and the output level changes from a high level to a low level, and the turn-off time when the output transistor Q3 is turned off and the output level changes from a low level to a high level. Almost equal. Therefore, if a circuit in which one delay time is clearly slower or faster than the other delay time is required, it is not desirable to use the circuit shown in FIG. 1.

For example, in a logic circuit consisting of a so-called 3-state output circuit that can take three states: "1" level, "0" level, and "high impedance" and its output control circuit, the output is "1" or " Speed up the time tpHZ and tpLZ to change from "0" level to "high impedance" state, and conversely change the output from "high impedance" state to "1" or "0".
It is often necessary to slow down the time tpZH and tpZL change to the level. In such a case, instead of using the circuit shown in Fig. 1 as the output control circuit, a total of three gate circuits, two inverters and a NOR circuit, are configured as shown in Fig. 2 to achieve a 3-state control circuit. Control the circuit. That is, inverter 2
This function is often achieved by using the delay time of the stages.

As mentioned above, at least two additional gates are required to provide a difference in delay time between the two.

The purpose of this invention is to make the turn-off time when the output changes from low level to high level constant with respect to the turn-on time when the output changes from high level to low level by simply adding a few elements to a normal saturation type logic circuit. An object of the present invention is to provide a bipolar saturation type logic circuit that provides an output having a delay time.

According to the present invention, there is provided a first transistor whose base is connected to an input terminal and whose collector is connected to one terminal of a power supply via a load; a second transistor connected to one terminal of the power supply and having its emitter connected to the output terminal; a second transistor having its base connected to the emitter of the first transistor, its emitter connected to the other terminal of the power supply and its collector connected to the output terminal; a fourth transistor whose emitter is connected to the collector of the first transistor and whose base is connected to one terminal of the power supply via the first resistor;
A fifth transistor whose base is DC connected to the collector of the fourth transistor, whose emitter is DC connected to the other terminal of the power supply, and whose collector is connected to one terminal of the power supply via the second resistor. By having a transistor, a diode connected between the base of the third transistor and the collector of the fifth transistor, and having a capacitive component between the collector of the fourth transistor and the ground point, 1st
After a predetermined time after the third transistor is turned off, the third transistor is turned off.
A bipolar saturation type logic circuit is obtained, which is characterized in that the transistors are turned off.

Next, embodiments of the present invention will be described.

Figure 3 is a circuit connection diagram showing one embodiment of the present invention, in which the present invention is applied to a TTL NAND circuit, but the emitter of transistor Q ₇ is newly connected to collector 3 of phase division stage transistor Q ₂ . The base of transistor _Q7 is connected to power supply 6 through resistor _R7 , and the collector is connected to transistor Q8.
connected directly to the base of the capacitor C
It is grounded via 1. The emitter of the transistor Q ₈ is grounded through the level shift diode D ₁ , the collector is connected to the power supply 6 through the resistor R ₈ ,
It is also connected to a connection point 4 between the emitter of the transistor Q ₂ and the base of the transistor Q ₃ via a diode D ₂ . i.e. output transistor Q ₃
At the base (control electrode) of, in parallel with the phase-dividing stage transistor Q ₂ , means are provided for supplying current by means of a resistor R ₈ and a diode D ₂ .

In Fig. 3, when input 1 is at the "1" level, both transistors Q ₂ and Q ₃ are conducting, and the potential of 3 is VBEQ ₃ (on) + VCEQ ₂ (on).
(However, VBEQ ₃ (on) is the base-emitter voltage when transistor Q ₃ is conductive, and VCEQ ₂ (on) is the collector-emitter voltage when transistor Q ₂ is conductive.) Therefore, transistor Q ₇ is a conductive state,
Transistor Q ₈ is in the cut-off state, and the current i ₁ flowing through resistor R ₈ flows through diode D ₂ and is supplied to the base of output transistor Q ₃ .

Let us now consider the case where input 1 falls from the "1" level to the "0" level. In the conventional circuit shown in FIG. 1, transistors Q ₂ and Q ₃ are cut off relatively quickly, and the potential of output 5 is
It rises as collector 3 of _Q2 rises.

However, in the circuit of the present invention shown in FIG. 3, even if transistor Q ₂ is cut off, the current i ₁ remains until transistor Q ₈ switches from the cut-off state to the conduction state.
is still flowing to the base of transistor _Q3 ,
The output maintains the "0" level.

To explain in detail, when the transistor Q ₂ is cut off, the current i ₂ flowing through the resistor R ₇ first flows through the base-emitter path of the transistor Q ₇ , so the potential of the collector 3 of the transistor Q ₂ is changed to the resistor R 7. ₂ , and R ₇ . As this point rises, transistor Q ₇ gradually becomes a reverse transistor, and current i ₂ now flows through the base-collector path of transistor Q ₇ and between the collector of transistor Q 7 and ground. After the capacitance of the connected capacitor C1 is charged, the potential of the base 7 of the transistor Q8 rises. After that, the potential of 7 becomes VD ₁ (on) + VBEQ ₈
(on) (where VD ₁ (on) and VBEQ ₈ (on) are _the forward voltage of diode D ₁ and the base-emitter voltage of transistor Q ₈ when it is conductive, respectively). conducts, and the current _i1 bypasses and becomes the collector current of the transistor _Q8 , so the output transistor _Q3 is cut off.

Therefore, even if the transistor _Q2 is cut off, the potential of the output 5 does not rise following the potential of the collector 3 of the transistor _Q2 , but rises after a predetermined delay time.

That is, according to the circuit of the present invention, the output transistor is turned off later than the circuit shown in FIG. 1, and the turn-off time can be delayed accordingly. Further, by appropriately selecting the resistance values of the resistors R ₂ , R ₇ , and R ₈ and the capacitance value of the capacitor C ₁ , a desired delay time can be obtained. After input 1 changes from the "1" level to the "0" level and the above-mentioned predetermined delay time has elapsed, the transistor _Q2 is off, and the current _I1 from the resistor _R8 flows through the transistor _Q8.
There is no base current of transistor _Q3 , and transistor _Q3 is also off.
When the input 1 changes from the "0" level to the "1" level in this state, the transistor Q ₂ turns on and starts supplying base current to the transistor Q ₃ , so the transistor Q ₃ turns on. At this time, the resistance R ₈
The current from I ₁ is not yet flowing into the base of transistor Q ₃ , but transistor Q ₃ is a transistor
Since it is turned on by the current from _Q2 , this turn-on time is no different from the turn-on time of the conventional example shown in FIG.

This invention is applicable not only to TTL circuits but also to shortcut keys.
It can be applied to TTL, DTL circuits, or those in which shot key barrier clamps are provided as necessary to the transistors that make up the circuit.In addition to the aforementioned 3-state output control circuit, this circuit can also be used for It can be used in clock input circuits of sequential circuits that require a minimum clock pulse width.

As described above, the turn-off time can be easily delayed without delaying the output turn-on time by simply adding the above-mentioned element between the collector ground potential of the phase division stage transistor and the power supply. Therefore, there is no need to provide individual circuits as in the conventional case, and the number of elements constituting the circuit can be significantly reduced, which has a great effect.

[Brief explanation of drawings]

Fig. 1 is an example of a circuit connection diagram of a TTL NAND circuit, Fig. 2 is an example of a logic diagram of a 3-state output circuit and a circuit that controls it, and Fig. 3 is an example of a TTL NAND circuit showing an embodiment of the present invention. It is a connection diagram. Explanation of symbols, Q ₁ to Q ₈ ...transistor, D ₁ ,
D ₂ ... Diode, R ₁ to _{R 8} ... Resistor, 1 ... Input terminal, 5 ... Output terminal, 6 ... Power supply terminal.

Claims (1)

[Scope of utility model registration request] a first transistor having a base connected to an input terminal and a collector connected to one terminal of the power supply via a load; a base connected to the collector of the first transistor; a second transistor whose base is connected to the emitter of the first transistor, whose emitter is connected to the other terminal of the power supply, and whose collector is connected to the output terminal; a fourth transistor whose emitter is connected to the collector of the first transistor and whose base is connected to the one terminal of the power supply via a first resistor; a collector of the fourth transistor, an emitter connected to the other terminal of the power source, and a collector connected to the one terminal of the power source via a second resistor; a fifth transistor; a diode connected between the base of the third transistor and the collector of the fifth transistor; and a capacitive component between the collector of the fourth transistor and a ground point. A bipolar saturation type logic circuit, wherein the third transistor is turned off a predetermined time after the first transistor is turned off.