JPH073828Y2 - On-gate circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an on-gate circuit for supplying a higher gate current to a semiconductor device such as a thyristor including a gate turn-off thyristor.

[Technical Background of the Invention and its Problems] FIG. 5 shows a conventional on-gate circuit, which includes an on-gate power supply 1, a transistor 2, a steady on-gate resistor 3 (resistance value).
R ₃ ), a high-gate resistor 4 (resistance value R ₄ ), and a capacitor 5 (electrostatic capacitance C ₅ ), and 6 is a driven semiconductor. In this circuit, as shown in the time chart of FIG. 6, the transistor 2 is turned on by the ON signal and the current i ₁ corresponding to the steady ON gate current is passed through the resistor 3.
At the same time that the current flows, the higher gate current i ₂ flows through the resistor 4 and the capacitor 5, and the sum of i ₁ and i ₂ is supplied to the driven semiconductor 6 (i ₁ + i ₂ = i ₃ ). Then, when the ON signal is turned off, the current i ₃ supplied to the driven semiconductor 6 becomes zero,
At this time, since the electric charge is stored in the capacitor 5,
This charge is discharged through the resistors 4 and 3. In order to obtain a high gate current, for example, 20 to 30Ap by this method, it is necessary to make the capacitor 5 large and the resistor 4 small so as to secure a predetermined width. This can cause problems.

Further, in the conventional circuit, since the discharge of the capacitor 5 starts after the transistor 2 is turned off, the on signal-as shown in FIG.
When the ON signal interval (t ₂ −t ₁ ) is sufficiently longer than the discharge time constant (R ₃ + R ₄ ) C ₅ of the capacitor 5 (t ₂ −t ₁ becomes (R ₃ +
In the case of 3 to 4 times or more of R ₄ ) · C ₅ ), the charge of the capacitor 5 is sufficiently discharged, so that a normal higher gate current Ip ₁ can be obtained even when an ON signal is given at t = t _2. . On the other hand, as shown in FIG. 8, the ON signal-ON signal interval (t ₄ −
When t ₃ ) becomes short, the high-gate current Ip ₂ becomes smaller than the normal value Ip ₁ because the ON signal is input at t = t ₄ before the capacitor 5 is sufficiently discharged.

Therefore, in order to obtain the normal higher gate current Ip ₁ , the interval between the ON signal and the ON signal is the discharge time constant (R ₃ +
There is a problem that the operation speed of the gate circuit is limited because of the requirement of 3-4 times or more of R ₄ ) · C ₅ . This is a particularly important problem when it is desired to shorten the ON signal-ON signal as in the case of performing PWM control with an inverter or the like.

[Object of the Invention] An object of the present invention is to provide an on-gate circuit that can supply a normal high gate current even when the interval between the on-signal and the on-signal is short.

[Summary of the Invention] In order to achieve the above object, the present invention provides a switching element in each of a path through which a high gate current flows and a path through which a steady on-gate current flows. It is designed to be turned on only.

[Embodiment of the Invention] FIG. 1 shows the configuration of an embodiment of the present invention. In the figure,
Reference numeral 7 is a steady on-gate transistor, 9 is a steady on-gate resistor, 8 is a high-gate transistor, and 10 is a high-gate resistor. The transistor 8 is turned on / off by an output signal of the single-shot pulse generation circuit 11.

The operation of FIG. 1 will be described below with reference to the time chart of FIG.

When the ON signal is input, the transistor 7 is turned ON and the current i ₁ corresponding to the steady ON gate current flows through the resistor 9. At the same time, the ON signal outputs the higher gate signal of the time width tW from the single pulse generation circuit 11 and the transistor 8 Is turned on, a current i ₂ corresponding to a higher gate current flows through the resistor 10, and the sum i ₁ + i ₂ = i _{3 of} these is supplied to the driven semiconductor 6. The transistor 8 turns off after a time tW and i ₃ = i ₁ , and when the on signal turns off at t = t ₅ , the transistor 7 also turns off and i ₃ = 0. At this time, since there is nothing in the circuit that discharges like the capacitor 5 in FIG. 5, even if the ON signal-ON signal interval t ₆ -t ₅ is short, the ON signal at t = t ₆ produces a normal high gate current Ip. Is obtained. Therefore, the high speed operation of the on-gate circuit becomes possible.

Further, in FIG. 5, the relationship between the peak current of the higher gate current and the time width tW is not independent. For example, if the value of the resistor 4 is reduced, the peak current increases, but the higher gate time constant R ₄
・ Time width tW becomes shorter because C ₅ becomes shorter. On the other hand, in Fig. 1, the peak current changes when the value of resistor 10 is changed.
Although Ip changes, the time width tW does not change because it is determined by the single pulse generation circuit 11. Therefore, the present invention also has the advantage that the higher gate peak current Ip and the time width tW can be set independently.

In FIG. 1, the transistor 7 and the transistor 8
Is represented by a pnp bipolar transistor, but an npn bipolar transistor or a field effect transistor (FE
In principle, there is no change in T), or a parallel connection of these.

Another embodiment according to the present invention is shown in FIG. 12, 14 are transistors and resistors for steady on-gate, 13 and 15 are transistors and resistors for higher gate, and the transistor 12 is turned on by the ON signal and the monostable multivibrator 16 generates a single-shot pulse of a predetermined width. Transistor 13 turns on and the higher gate current is supplied to thyristor 21.
Supply to.

Still another embodiment of the present invention is shown in FIG. FIG. 4 shows the present invention applied to the gate circuit of the gate turn-off thyristor 22. 24 and 25 are FETs for steady on-gate and 23 are resistors.
Is a transistor for driving the FET 24, 27 and 28 are FETs for a high gate, and 26 is a transistor for driving the FET 27, and 38 is a resistor.
Is a power supply for giving a negative bias to the gate turn-off thyristor 22, 40 is its series resistance, and 41 is an off-gate circuit. Transistor 23 turns on by the ON signal and FET2
A current corresponding to a steady-state on-gate current flows through the resistor 4 and a pulsed ON signal is given to the transistor 26 through the resistor 32 and the capacitor 33, and the transistor 26 is turned on for a predetermined time to drive the FET 27 and drive the resistor. A current corresponding to a high gate flows through 28 and drives the gate turn-off thyristor 22. In this example, when the ON signal disappears, the electric charge is stored in the capacitor 33, which is discharged through the diode 39 and the resistors 29, 30, 34. However, this discharge time becomes 1/10 to 1/100 or less of the discharge time of the capacitor 5 shown in FIG. Since various circuits can be applied to the off-gate circuit 41, description thereof will be omitted.

[Advantage of the Invention] According to the present invention, since the discharge time of the capacitor used in the higher gate circuit is not present or can be ignored, the ON signal-ON signal interval can be shortened and the ON gate circuit can operate at high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a time chart showing an operation of FIG. 1, FIG. 3 is a configuration diagram of another embodiment according to the present invention, and FIG. 4 is a book. FIG. 5 is a view showing still another embodiment according to the invention, FIG. 5 is a view showing a configuration of a conventional example, and FIG.
FIG. 8 to FIG. 8 are time charts showing the operation of FIG. 1 ... on-gate power supply, 2 ... transistor, 3,9,14,2
5 …… Steady on-gate resistance, 4, 10, 15, 28 …… Higher gate resistance, 5 …… Higher gate capacitor, 6 ……
Driven semiconductor, 7, 12 …… Steady on-gate transistor, 8, 13 …… Higher gate transistor, 11 …… Single pulse generator circuit, 16 …… Monostable multivibrator, 21
...... Thyristor, 24 …… Steady on-gate FET, 27 …… Higher gate FET, 22 …… Gate turn-off thyristor, 23,26 …… Transistor, 38 …… Negative bias power supply, 4
0 …… Negative bias series resistance, 41 …… Off gate circuit, 17,
18,19,20,29,30,31,32,34,35,36,37 …… resistance, 39 …… diode, 33 …… capacitor.

Claims (1)

[Scope of utility model registration request] 1. An on-gate power supply whose negative electrode terminal is connected to a cathode terminal of a power semiconductor device, and a steady on-gate device which is turned on by an on signal provided between a positive electrode terminal of the on-gate power supply device and a gate terminal of the power semiconductor device. A steady on-gate circuit comprising a switching element and a steady on-gate resistor connected in series to the steady on-gate switching element, and a high-gate switching element which is turned on for a predetermined period when the on signal is given through a single pulse generation circuit. An on-gate circuit comprising a high-gate circuit composed of a high-gate resistor connected in series to the high-gate switching element and having a resistance value lower than that of the steady on-gate resistor.