JPS5915331A - Logical gate circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a logical gate circuit, by preventing a large current which is instantaneously generated when the power supply voltage reaches the minimum value at which the logical gate circuit can be actuated during a rise of the power supply circuit. CONSTITUTION:A transistor TR16 is turned on when the power supply voltage VCC applied to a terminal 14 rises up to the base-emitter voltage VBEQ16 of the TR16. In this case, a TR9 is kept off. Then a TR5 is turned on when the voltage VCC rises up more and exceeds the base-emitter voltage (VBEQ5)+VCEQ16. In this case, the TR16 and TR9 are on and off respectively with TRQ17, 18 and 19 turned off respectively. Therefore, the TR9 is not turned on at a time point when the voltage VCC rise up to turn on the TR5. This circuit avoid flowing a large power supply current ICC. As a result, no evil effect is given to the operation of a system using a logical gate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to logic gate circuits, especially KDTL (diode transistor logic) or TTL (transistor logic).
The invention relates to saturated bipolar logic circuits including transistor logic.

FIG. 1 is a circuit diagram showing a typical example of a conventional TTL. 1 is an input terminal, 2 is a Schottky barrier diode, 5 is a phase inversion transistor, 9 is an output transistor, 11tJ two-level shift transistor, and 13 is a buffer transistor which is connected to the transistor 11 in Darlington to form an output buffer circuit. A pull-down circuit is composed of 8 pull-down transistors together with resistors 6 and 7. 14 is a power supply terminal, 15 is an output terminal, 3 + 4 r
6 r 7 +10.12 is the resistance.

The power supply voltage of such a TTL circuit (hereinafter abbreviated as VCC)
The change in the power supply current (hereinafter abbreviated as IOC) with respect to the following equation 9 is as follows.

VCC is the transistor 50 pace-emitter voltage (v
nzqs ) (!: ) If it is smaller than the sum of the base-emitter voltage (VBF, Qg) of RangeMeta 9. . does not flow. VCC increases and VYQ5 + VBF, QI
When the transistor 5 and the transistor 9 reach the conductive state, the I
CC starts playing. At this time, the collector potential of transistor 5 changes from VCC to the collector-emitter voltage of transistor 5 (VCEQ5) +VB (~, transistors 11 and 13 are cut off, but transistors 5 and 9 are turned on). , the collector potential of transistor 5 is a value sufficient to turn off transistors 11 and 23 (VBEQII" vBEQ13+VC
Transistors 11° and 1
3 is in a conductive state. Therefore, a low impedance current path is created between the CC and the OND through the resistor 12 and the transistors 11 and 13.9, so that a very large current momentarily flows.

Further, this current is particularly large when the off-buffer resistance 12 is small, such as in a driver, a buffer, etc., and there is a possibility that it exceeds the maximum ICC value in actual use.

When configuring a system using such a logic circuit, this instantaneous large current is required to operate the system when the power is turned on,
If the device is used in a place where it is frequently turned off, it may have negative effects such as a reduction in the lifespan and malfunction of other ICs due to noise generation.

As mentioned above, in the conventional logic gate circuit shown in FIG. This has the disadvantage that it adversely affects the operation of the system using the gate.

The present invention has been made in view of the above circumstances, and provides a logic gate circuit that prevents the phenomenon in which a large current flows at the moment when the current and voltage increase, which occurs in conventional circuits, the value reaches the minimum operable value of the logic gate circuit. The purpose is to provide

According to the present invention, a phase inversion transistor is inserted between an input gate circuit consisting of a diode or a transistor and a common emitter output transistor, and an output buffer is inserted between the collector of the phase inversion transistor and the collector of the previous We output transistor. In a logic gate circuit having an output buffer circuit including a transistor, when the power supply voltage is lower than the minimum voltage at which the logic gate circuit can operate, it is in a conductive state K, and when it is higher than the minimum voltage, it is in a cutoff state. The output signal of the emitter-grounded transistor whose base is biased controls the cut-off or conduction of the output transistor of the logic circuit, thereby providing a logic gate circuit that does not generate an instantaneous large current when the power supply voltage rises.

FIG. 2 is a circuit diagram showing an embodiment of the present invention. The difference from the conventional circuit shown in FIG. 1 is that the collector is connected to the base of the output transistor 9, and the transistors 17, 18
．． 19 and a common emitter transistor 16 with a base bias circuit consisting of resistors 20, 21, 22, and 23.

The operation of the TTL of the present invention will be described below.

When the power supply voltage (Vcc) is less than the base-emitter voltage (BFQ+c+) of the transistor 16, the power supply current (...) does not flow.When VCC rises and reaches 16 vB, the transistor 16 connects the entire resistor 23. Since the base of transistor 9 is connected to the collector of transistor 16, while transistor 16 is in conduction, the base potential is equal to the collector-emitter voltage (VCE) of transistor 16.
Q16) and maintains the cut-off state. Further, Vcc increases and the base-emitter voltage of transistor 5 (VBEQ
II) When +VCEQ16 is exceeded, transistor 5 becomes conductive. At this time, the transistor 16 is in a conductive state.
Transistor 9 is in a cut-off state, transistors 17, 18 .
19 is also in a blocked state. In the conventional circuit, VCC rises and transistor 5 becomes conductive, and at the same time transistor 9 becomes conductive.
Since transistors 11 and 13 also become conductive until the collector potential of transistor 5 falls, a large IOC momentarily flows, but with the circuit of the present invention, I/
At the time when 1Vcc rises and transistor 5 becomes conductive, transistor 9 does not become conductive, so no large IOC flows. When VCC further increases and reaches the sum of the base-emitter voltages of transistors 17, 18, 190, VBEQ 17 + VBEQ, + VHEQ19, transistors 17, 18, and 19 become conductive, so that the base potential of transistor 16 increases between the collector and emitter of transistor 17. Voltage V. . It drops to Q17 and enters the cut-off state. When the transistor 16 enters the cut-off state, the transistor 9, which has been cut off, is supplied with base current from the transistor 5, and becomes conductive for the first time.

At this time, the transistor 16 is in a cut-off state, so 1 to 1
It does not affect the operation of the logic gate circuit consisting of 5.

FIG. 3 is a circuit diagram illustrating another embodiment of the invention, in which the collector of transistor 16 is connected, preferably via Schottky diodes 24, 24', to the bases of output transistors 9, 9' of a plurality of logic gate circuits, respectively. This is what I did. The diodes 24 and 24' are unidirectional elements inserted to prevent interference between logic gate circuits during operation, and are an OR circuit.
) and the voltage (
The type of output transistor does not matter as long as the sum (vF+Vc0) with VCIQ 16 ) is smaller than the base-emitter voltage (vBE9) of the output transistor.

The effects of this embodiment are the same as those of the first embodiment described above, and also have the effect of simplifying the circuit configuration when a plurality of logic to gate circuits are included.

As described above, according to the present invention, the generation of an instantaneous large current that occurs when the power supply voltage rises and the value reaches the lowest value I7 in which the logic gate circuit can operate is prevented, so the logic gate This has the effect of improving circuit reliability.

[Brief explanation of drawings]

Figure 1 is a circuit connection diagram showing a typical example of conventional TTL, Figure 2
The figure is a circuit connection diagram showing one embodiment of the logic gate circuit of the invention, and FIG. 3 is a circuit connection diagram showing another embodiment of the logic gate circuit of the invention. 1... Input terminal section, 2... Input Schottky barrier diode, 3, 4, 6, 7, 10, 12
゜20.21.22.23...Resistance, 5.8,
9゜11.13, 16, 17, 18, 19.9'...
・・・Transistor, 24.24'・°°Paper Schottky barrier diode, 14...Power terminal, 1
5... Output terminal.

Claims (1)

[Claims] A phase inversion transistor is inserted between an input gate circuit consisting of a diode or a transistor and an emitter-grounded output transistor, and an output buffer transistor is provided between the collector of the phase inversion transistor and the collector of the output transistor. In a logic gate circuit having a circuit, the base is biased so that when the power supply voltage is lower than the minimum voltage at which the logic gate circuit can operate, it is in a conductive state, and when it is higher than the minimum voltage, it is in a cutoff state. 1. A logic gate circuit comprising means for controlling cut-off or conduction of an output transistor of the logic circuit using an output signal of a transistor whose emitter is grounded.