JPS5975714A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To obtain a settable FF circuit which consumes less power and consists of a small number of elements by connecting the emitters of the 1st and the 2nd TRs to the common emitters of couples of TRs for writing and holding and connecting the bases and collectors of both TRs in common, and supplying a setting signal to the bases and connecting the collectors to a resistance on a complementary side. CONSTITUTION:Transistors TRs 7 and 10 are provided for writing and TRs 8 and 9 are provided for holding. The setting signal is supplied to the bases of TRs 4 and 5 and the collectors are connected to the resistance 1 on the complementary side to turn a TR12 on and a TR13 off when a clock signal In3 is at a high potential; when a clock signal In3 is held at the high potential, TRs 12 and 13 turn on and off respectively and when a set input terminal In2 is held at the high potential, the TRs 4 and 10 always turn on and off respectively regardless of whether a data input terminal In1 is at the high or low potential, thereby holding an acknowledge terminal Out1 and a negative acknowledge terminal Out1' at the high potential and low potential respectively. Thus, when the setting signal In2 goes up to the high potential, a current flows through the complementary-side resistance 1 and TRs 4 and 5, so the function of the settable FF is obtained regardless of whether the clock is in data holding or writing mode.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current switching type 7/70 circuit using vertical logic.

A conventional and widely known flip-flop circuit with a current switching type set is shown in FIG. The operation of the circuit in Figure 1 can be explained in the second diagram.
This will be explained using the waveform diagram in the figure. At timing TO, the clock input terminal 1n3 is at the high voltage level 7, so the transistors 3 and 14- are in a conductive state, and the transistor 15 is in a disconnected state.Since the set input terminal In2 is at a low potential, the transistors 4, 5, and 12 is in the cutoff state, the transistor 13 is in the conduction state, and since the data input terminal 1nl is at a high potential, the transistor 7 is in the conduction state and the transistor IO is in the cutoff state.
Current flows through transistors 7.13.14, the positive output terminal Qutl is at a high potential and the negative output terminal σut'l is at a low potential. Next, at timing T1, when the data input terminal 1nl becomes a low potential, the transistor 7 is cut off and the transistor io is turned on, so that the current that had been flowing through the resistor 1' stops flowing, and now the resistor 2.
Transistor lO, 13, 14vI - constant current source 1
1 current flows, and the positive output terminal (Jutl is at the low voltage level 1, and the negative output terminal 0utl is at the high N level) At timing T2, when the clock input terminal 1n3 becomes low potential, the transistor 3.14 becomes cut off. Until now, the negative output terminal (Jutl) was at a high potential, so the transistor 8 was cut off, the transistor 9.15 was turned on, and the current of the constant current source 11 was changed to the resistance 2.transistor 9.15.
', the positive output terminal 0utl and the negative output terminal 0utl are the same as the previous state, and the positive output terminal 0u
t1 has a low potential, and the negative output terminal 0utl has a high potential.

When set input terminal chain n2 becomes high potential at timing T3, transistor 4. 5. 6.12°14 is in the conductive state, the transistor IL13115 is in the cutoff state, and the resistor 1.12 is in the conductive state. ) Ranjistaro, 12°14'? The current of the constant current source 11 flows through the positive output terminal 0utl.
has a high potential and the negative output terminal Out 1 has a low potential.5 When the set input terminal 1n2 becomes a low potential at timing T4, the transistor 3.14 is cut off because the clock input terminal In3 is at a low potential.

The transistor 15 becomes conductive, and since the positive output terminal 0utl has been at a high potential until now, the transistor 8 is conductive, and the transistor 9V is also cut off, so that the current of the constant current source II flows through the resistors 1. The current flows through the transistor 8.15', and the positive output terminal Out 1 is at a high potential, and the negative output terminal Outl is at a constant potential.

Therefore, by connecting data signals to the terminal 1nl, set signals to the terminal In2, and clock signals to the terminal In3, the function of a flip-flop with set can be obtained. However, the conventional 7-lip-flop circuit has many current sources? However, the disadvantages are that the power consumption and the number of elements are large.

The purpose of the present invention is to provide a clip with low power consumption and low number of elements.
5. To provide a flop circuit A flip-flop circuit according to the present invention has the emitters of a first transistor all connected to the common emitter of a set of transistors for data writing, and the emitters of a second transistor connected to the common emitter of a set of transistors for data retention.
The emitters of the transistors are all connected, the bases of the first and second transistors are connected in common, the collectors are also connected in common, a cent signal is given to the base, and the collector is connected to the complementary side resistor that generates the output voltage sound. By connecting this connection, when the cent signal becomes high potential, current flows through the complementary side resistor and through this first or second transistor, regardless of whether the clock is in the data retention or data write state. A flip-flop is a set slip whose state is set.
You can get the flop function.

Next, the present invention will be fully explained using the drawings.

FIG. 3 shows a circuit diagram showing a preferred embodiment of the invention. The emitters of the first transistor 4 are connected to the common emitters of the data writing transistors 7.10, and the emitters of the second transistors 5 are all connected to the common emitters of the data holding transistors 8.9. Give a cent signal to the bases of the second transistors 4 and 5,
By connecting the collector to the resistor l on the complementary side, when the clock signal In3 is at a high potential, the transistor 12 is in a conductive state and the transistor 13 is in a cut-off state, and when the set input terminal In2 is at a high potential, the data input terminal 1nl is at a high potential. , in both states of low potential, transistor 4 is always in a conductive state and transistor IO is in a cut-off state, so that the terminal 0utl becomes a high current leakage terminal 0u.
tl becomes a low potential. Further, when the terminal In3 is at a low potential, the transistor 12 is in a cutoff state and the transistor 13 is in a conduction state, and when the terminal 0utl is in a high potential in the previous state and the transistor 8 is in a conduction state and the transistor 9 is in a cutoff state, the transistor 5 is also in a cutoff state. Conductive state p1 terminal 0
utl is at a high level, and the terminal 0utl is at a low potential.In the previous state, when 0utl was at a low potential and transistor 8 was in the cutoff state and transistor 9 was in the conductive state, transistor 5 first began to conduct and a current flowed through resistor l. After the current begins to flow, the base potential of transistor 9 becomes low and transistor 9 goes into a cut-off state.Therefore, transistor 8 goes into a conduction state and then transistor 9 is completely cut off.

Transistor 5.7 becomes 0u by becoming conductive.
tl is a high potential, and 0utl is a low potential.

As described above, according to the present invention, it is possible to obtain a set clip-flop circuit with low power consumption and a small number of elements.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a waveform diagram showing the operation of FIG. 1, and FIG. 3 is a circuit diagram showing a preferred embodiment of the present invention. 1, 2...Resistor, 3-15...Transistor, If, I2. I3... Constant current source, I
nl...Data input terminal, 1n2...
Set input terminal, In3...Clock input terminal, 0utl...Positive output terminal, 0utl...
...Negation output terminal. 1st ward 箭 7th ward Taimi) gu・To million Tz Ts Tt
◆ number (I ψ

Claims (1)

[Claims] The emitter of a first transistor is connected to the common emitter of a transistor set for data writing, the emitters of a second transistor are all connected to the common emitter of a data holding transistor set, and and the base gold of the second transistor are commonly connected. A slip-flop circuit characterized in that the collectors are also connected in common, a set signal is applied to the base, and the collector is connected to a complementary side resistor that generates an output voltage.