JPS6142898B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a three-state circuit used in a transmission line drive circuit of a data transmission system.

A 3-state circuit is a circuit that has three output levels: high level, low level, and high impedance state, and the outputs of multiple drive circuits are connected to use one transmission line as a common line. When one drive circuit is driving a common line, setting the output of the other drive circuit to a high impedance state will prevent damage to the drive circuit and adverse effects on the transmission signal due to interaction between the drive circuits. This is a circuit designed to avoid this.

An example of a conventional three-state circuit is shown in FIG.

In the circuit shown in Figure 1, a voltage of 5V is applied to the power supply terminal Vcc, and the input terminals I ₁ , I ₂ and strobe signal input terminal S are at normal TTL logic levels (low level ≒ 0.2V, high level ≒ 3.5V). ) is applied to perform a logical operation. Here, the transistor
Except for _Q5 , Schottky-type transistors are used. When a high level is input to the strobe signal input terminal S, diodes D1 and D3 and transistors Q8 and Q9 are off, and the circuit as a whole functions as a normal two-input OR circuit with no input to input terminals I1 and I2. It operates according to the level of the signal being received. In other words, when a low level of 0.2V is applied to both input terminals I1 and I2, diodes D2 and D4
turns on and lowers the base potential of transistors Q1 and Q2 by about 0.6V, so transistors Q1 and Q2 turn off. Since the common collectors of transistors Q1 and Q2 are connected to the power supply terminal Vcc via resistor R3, the potential of the base of phase division stage transistor Q3 connected to this common collector is approximately 1.5V.
The phase dividing stage transistor Q3 is turned on, the emitter potential rises to about 0.7V, and the collector potential drops to about 1V. As a result, the output transistor Q6 whose base is connected to the emitter of the phase division stage transistor Q3 is turned on, and the transistor Q4 whose base is connected to the collector of the phase division stage transistor Q3 and whose base is connected to the emitter of the transistor Q4 and whose collector is turned on. Both transistors of the off-buffer circuit consisting of the collector of the transistor Q4 and the commonly connected transistor Q5 are turned off, and approximately 0.2V is applied to the output terminal X connected to the common connection point between the emitter of the transistor Q5 and the collector of the output transistor Q6. low level is output. In addition, either one of the input terminals I1 or I2,
Alternatively, when a high level (3.5V) is applied to both, the diode connected to the input terminal to which the high level is input turns off, one or both of transistors Q1 and Q2 turns on, and the phase division stage transistor Q3 The base potential drops to about 1.1V, the phase division stage transistor Q3 turns off, the emitter potential drops, and the collector potential rises to near the voltage of the power supply terminal Vcc, 5V. This turns off the output transistor, and the off-buffer circuit is connected to the power supply terminal.
Vcc potential 5V is approximately 2V _F (V _F is transistor Q
4. The voltage between the base and emitter of Q5 is approximately 0.75V)
, and a high level of approximately 3.5V is output to output terminal X.

When a low level is input to the strobe signal input terminal S, diodes D1 and D3 and transistors Q8 and Q9 are turned on. That is, diode D
1, by turning on D3, the transistor Q
The base potential of transistors Q1 and Q2 drops to approximately 0.6V, transistors Q1 and Q2 are turned off regardless of the level input to input terminals I1 and I2, and transistor Q
8 and Q9 are turned on, the potentials at nodes b and c are lowered to about 0.6V, respectively, and the phase division stage transistor Q3, the output transistor Q6, and the off-buffer circuit transistors Q4 and Q5 are all turned off, and the output terminal X becomes high. set to impedance.

As mentioned above, in the conventional three-state circuit shown in FIG. 1, the configuration of the high impedance setting circuit required to set the output terminal X to the high impedance state includes the diode D1, as shown in FIG.
D3, transistors Q8, Q9, resistors R1, R2
Six elements are required. Also, considering the propagation delay time, since the collectors of transistors Q8 and Q9 are connected to nodes b and c, the Ccs of transistors Q8 and Q9 is shorter than that of a normal gate circuit.
(Collector-substrate capacitance) increases the parasitic capacitance connected to nodes b and e, and the propagation delay time also slows down accordingly.

An object of the present invention is to provide a three-state circuit with a reduced number of elements and a faster propagation delay time.

The three-state circuit according to the present invention includes a first transistor whose collector is connected to an output terminal and whose emitter is connected to a first power supply, and a second transistor whose emitter is connected to the output terminal and whose collector is connected to a second transistor through a first resistor. A second transistor is connected to the power supply of the first transistor, one of its emitters is connected to the base of the first transistor, one of the other emitters is connected to the strobe signal input terminal, and the collector is connected to the second transistor through a second resistor. a third transistor having a multi-emitter structure connected to a power supply of the strobe signal, and a connecting means for connecting the collector of the third transistor and the base of the second transistor, and the strobe signal is input to the strobe signal input terminal. When the signal level is at a first level, the first and second transistors are not made conductive, and only the third transistor is made conductive;
When the signal level input to the strobe signal input terminal is at a second level, the first, second, and third transistors are made conductive or nonconductive depending on the signal level input to the base of the third transistor. It is characterized by:

FIG. 2 is a circuit diagram showing a three-state circuit according to one embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same symbols. Here, a multi-emitter transistor Q10 is used in the phase division stage of a normal two-input OR circuit, one emitter E1 is connected to the base of the output transistor Q6, and the other emitter E2 connects the output terminal The strobe signal input terminal S is connected to the strobe signal input terminal S into which the strobe signal for setting is input, and this strobe signal input terminal S is connected to the cathode side of the diodes D1 and D3, and the anode side of the diodes D1 and D3 are connected to the bases of the transistors Q1 and Q2, respectively. This is the circuit connected to.

The circuit of FIG. 2 operates as follows.

When a high level is input to the strobe signal input terminal S, the diodes D1 and D3 are turned off, and the emitter E2 of the phase division stage transistor Q10 is at a high level, so the operation of Q10 is determined by its base potential. . Therefore, the entire circuit operates as a normal two-input OR circuit in accordance with the signal level input to the input terminals I1 and I2. When a low level is input to the strobe signal input terminal S, diodes D1 and D3 are turned on, and the base potential of transistors Q1 and Q2 drops to approximately 0.6V.
Regardless of the level input to the input terminals I1 and I2, the transistors Q1 and Q2 are turned off, so the potential at node C rises. At this time, the strobe signal input terminal S, that is, the emitter E2 of one of the phase division stage transistors Q10, is low. level (0.2V), so the potential of node C is about 1.0V and transistor Q10
is turned on. Therefore, the base current and collector current of the transistor Q10 flow into the strobe signal input terminal S through the emitter E2, and no current flows into the base of the output transistor Q6, so that the output transistor Q6 is turned off. Also, since the phase division stage transistor Q10 is on, the potential at the node b drops to about 0.6V, and the transistors Q4 and Q5 of the off-buffer circuit are also turned off. Therefore, the output terminal X is set to a high impedance state.

As mentioned above, similarly to the circuit shown in FIG. 1, the circuit shown in FIG. 2 operates as a two-input OR circuit when the strobe signal input terminal S is at a high level, and the strobe signal input terminal S is at a low level. At this time, the output terminal X is set to a high impedance state. Moreover, in the case of Fig. 2, the diode D is used to set the output terminal X to a high impedance state.
1, D3, and one element E2 of the multi-emitter transistor Q10, and the number of elements can be greatly reduced compared to the conventional circuit shown in FIG. Also regarding the propagation delay time, nodes b and c
Since the number of transistors connected to nodes B and C is reduced, the parasitic capacitance due to Ccs attached to nodes b and c can also be reduced, resulting in a significant improvement.

The feature of the present invention is that a low level signal is applied to one of the emitters of a phase division stage transistor having a multi-emitter structure, and the output transistor connected to the next stage is turned on at a base potential lower than the base potential during normal operation. , and the off-buffer circuit are turned off to set the level at the connection point between the output transistor and the off-buffer circuit to a high impedance state. Therefore, the circuit shown in FIG. 2 is one example, and circuits having the above characteristics are within the scope of this patent.

[Brief explanation of the drawing]

FIG. 1 shows a conventional three-state circuit, and FIG. 2 shows one embodiment of the three-state circuit according to the present invention. D1, D2, D3, D4, D5...Diode, Q1, Q2, Q3, Q4, Q5, Q6, Q
7, Q8, Q9...transistor, Q10...multi-emitter transistor, R1, R2, R3,
R4, R5, R6, R7, R8...Resistance, I1,
I2...Input terminal, S...Strobe signal input terminal, X...Output terminal, Vcc...Power supply terminal, E1,
E2... Emitsuta.

Claims (1)

[Claims] 1 a first transistor whose collector is connected to the output terminal and whose emitter is connected to a first power supply;
A second transistor is connected to a second power supply through a resistor, one of its emitters is connected to the base of the first transistor, one of the other emitters is connected to a strobe signal input terminal, and the collector is connected to the second transistor. a third transistor with a multi-emitter structure connected to a second power supply via a resistor;
connecting means for connecting the collector of the transistor and the base of the second transistor, and connecting the first and second transistors when the signal level input to the strobe signal input terminal is at a first level. When the signal level input to the strobe signal input terminal is at the second level, the first , a three-state circuit characterized in that the second and third transistors are conductive or non-conductive.