JPH0231528B2 - - Google Patents
Info
- Publication number
- JPH0231528B2 JPH0231528B2 JP58143363A JP14336383A JPH0231528B2 JP H0231528 B2 JPH0231528 B2 JP H0231528B2 JP 58143363 A JP58143363 A JP 58143363A JP 14336383 A JP14336383 A JP 14336383A JP H0231528 B2 JPH0231528 B2 JP H0231528B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- base
- reset
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000295 complement effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
- H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
本発明は、電流切換型論理回路によるセツト＝
リセツト フリツプフロツプに関する。[Detailed Description of the Invention] The present invention provides a set =
Reset Regarding flip-flops.
セツト信号及びリセツト信号の入力によつて任
意にセツト又はリセツト状態に遷移し得る、所謂
セツト＝リセツト フリツプフロツプを電流切換
型論理回路で構成する場合、第１図に示す回路が
従来より使用されている。第１図の従来回路のセ
ツト＝リセツト フリツプフロツプの動作を簡単
に説明する。まずセツト信号Ｓが「Ｈ」レベルに
あり、一方、リセツト信号Ｒが「Ｌ」レベルにあ
るとき、トランジスタQAがON、トランジスタQD
がOFFし、定電流源IOの電流は、トランジスタ
QAを主に流れる。従つて、負荷抵抗RL1の電圧降
下により相補出力には「Ｌ」レベルが出力
され、一方、負荷抵抗RL2では電圧降下が生じな
いから、真値出力OUTには「Ｈ」レベルが出力
され、即ち「セツト」された状態となる。次にセ
ツト入力Ｓ及びリセツト入力Ｒが、上記状態から
共に「Ｌ」レベルになつた場合、トランジスタ
QAはONからOFFへ変化する。 When a so-called set-reset flip-flop is configured with a current switching type logic circuit, which can arbitrarily transition to a set or reset state by inputting a set signal and a reset signal, the circuit shown in Fig. 1 has been conventionally used. . The operation of the set-reset flip-flop of the conventional circuit shown in FIG. 1 will be briefly explained. First, when the set signal S is at the "H" level and the reset signal R is at the "L" level, the transistor Q A is turned on and the transistor Q D is turned on.
is turned OFF, and the current of the constant current source I O flows through the transistor
Mainly QA . Therefore, due to the voltage drop across the load resistor R L1 , a "L" level is output to the complementary output, whereas since no voltage drop occurs across the load resistor R L2 , a "H" level is output to the true value output OUT. In other words, it is in a "set" state. Next, when the set input S and reset input R both go to "L" level from the above state, the transistor
Q A changes from ON to OFF.
一方、トランジスタQBのベースは、その直前
の状態で「Ｈ」レベルとなつている負荷抵抗RL2
に接続されているからON状態であり、他のすべ
てのトランジスタがOFFとなつているから、定
電流源IOの電流はトランジスタQBのみを流れる。 On the other hand, the base of the transistor Q B is connected to the load resistor R L2 , which is at the "H" level in the previous state.
Since it is connected to the transistor QB, it is in the ON state, and all other transistors are OFF, so the current from the constant current source IO flows only through the transistor QB .
従つて負荷抵抗RL1には引き続き電流が流れ、
先の状態が保持される。即ちデータのホールド状
態となる。更に、リセツト入力「Ｒ」のみ「Ｈ」
レベルとすると、前述の動作と逆に、電流はRL2
→QD→IOと流れ、相補出力が「Ｈ」、真値出
力OUTが「Ｌ」の、「リセツト」状態となる。 Therefore, current continues to flow through the load resistor R L1 ,
The previous state is retained. In other words, the data is held. Furthermore, only the reset input “R” is “H”
In contrast to the operation described above, the current is R L2
→ Q D → I O , the complementary output is "H" and the true value output OUT is "L", resulting in a "reset" state.
第１図の回路は、簡単な構成と、論理レベルが
一種類即ち、所謂縦型構成でない為に、使用可能
電源範囲が広くとれる等の長所を有するものの、
セツト、リセツト信号に対するしきい値が、出力
電位の“Ｈ”レベルとなる為、高速動作や、LSI
内部配線通過による信号振幅の減衰のある場合に
セツト又はリセツトの確実性が低下する欠点があ
る。 The circuit shown in Fig. 1 has advantages such as a simple configuration and a wide usable power supply range because it has only one type of logic level, that is, it is not a so-called vertical configuration.
Since the threshold for set and reset signals is the "H" level of the output potential, high-speed operation and LSI
There is a drawback that the reliability of setting or resetting decreases when the signal amplitude is attenuated due to the passage of internal wiring.
本発明の目的は、上記欠点を除去し、安定動作
を実現する一方、従来回路からの大幅な素子数、
消費電力の増加のない電流切換型セツト＝リセツ
ト フリツプフロツプを提供する事にある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks and realize stable operation, while significantly increasing the number of elements from the conventional circuit.
The object of the present invention is to provide a current switching type set/reset flip-flop that does not increase power consumption.
本発明の電流切換型セツト＝リセツト フリツ
プフロツプは、ベースにセツト信号が入力される
第１のトランジスタと、ベースに基準電圧源が与
えられる第２のトランジスタと、ベースにリセツ
ト信号が入力される第３のトランジスタと、コレ
クタを該第１のトランジスタのコレクタに接続
し、エミツタを該第２のトランジスタのコレクタ
に接続した第４のトランジスタと、コレクタを該
第３のトランジスタのコレクタおよび該第４のト
ランジスタのベースに接続し、エミツタを該第２
のトランジスタのコレクタに接続しベースを該４
のトランジスタのコレクタに接続した第５のトラ
ンジスタと、該第４のトランジスタのコレクタに
接続される第１の負荷抵抗と、該第５のトランジ
スタのコレクタに接続される第２の負荷抵抗と、
前記第１，第２，第３のトランジスタのエミツタ
に接続される定電流源と、該第一のトランジスタ
のコレクタに接続され相補出力を得る第一のエミ
ツタフオロアと、該第三のトランジスタのコレク
タに接続され真値出力を得る第二のエミツタフオ
ロアとを有することを特徴とする。 The current switching type set-reset flip-flop of the present invention includes a first transistor to which a set signal is input to the base, a second transistor to which a reference voltage source is applied to the base, and a third transistor to which a reset signal is input to the base. a fourth transistor whose collector is connected to the collector of the first transistor and whose emitter is connected to the collector of the second transistor; whose collector is connected to the collector of the third transistor and the fourth transistor; Connect the emitter to the base of the second
Connect the base to the collector of the transistor of
a fifth transistor connected to the collector of the transistor, a first load resistor connected to the collector of the fourth transistor, and a second load resistor connected to the collector of the fifth transistor;
a constant current source connected to the emitters of the first, second, and third transistors, a first emitter follower connected to the collector of the first transistor to obtain a complementary output, and a collector of the third transistor; The second emitter follower is connected to obtain a true value output.
第２図に、本発明によるセツト＝リセツト フ
リツプフロツプの実施例の回路図を示す。同図
で、セツト信号入力端子Ｓ及び、リセツト信号入
力端子Ｒが共に低レベルのとき、トランジスタＱ
１とトランジスタＱ３は「OFF」となり、定電
流源IOによる電流は、トランジスタＱ２を通つ
て、トランジスタＱ４、トランジスタＱ５及び負
荷抵抗RL1，RL2によるデータ保持回路へ供給さ
れ、上記トランジスタＱ４及びＱ５のコレクタ電
位としてのデータを保持する。 FIG. 2 shows a circuit diagram of an embodiment of a set-reset flip-flop according to the present invention. In the same figure, when both the set signal input terminal S and the reset signal input terminal R are at low level, the transistor Q
1 and transistor Q3 are turned off, and the current from constant current source I O is supplied to the data holding circuit made up of transistor Q4, transistor Q5, and load resistors R L1 and R L2 through transistor Q2, and the current from transistor Q4 and transistor Q3 is turned off. Holds data as the collector potential of Q5.
ここで、セツト信号端子Ｓが高レベルに遷移し
た場合、トランジスタＱ２のベース電位即ち基準
電圧源VRの電圧値をしきい値として、トランジ
スタＱ１が「ON」となり、定電流源IOの電流は、
負荷抵抗RL1、トランジスタＱ１を通る様切換わ
り、従つてトランジスタＱ４のコレクタの電位は
低下し、一方、トランジスタＱ５のコレクタの電
位は上昇する。このとき、同図の様にトランジス
タＱ４，Ｑ５のコレクタにエミツタフオロアＱ
６，Ｑ７を接続し、それぞれのエミツタを各々相
補出力、真値出力OUTとすれば、真値出力
電位が高レベル、相補出力電位が低レベルのセツ
ト状態となる。 Here, when the set signal terminal S transitions to a high level, the base potential of the transistor Q2, that is, the voltage value of the reference voltage source V R is set as the threshold, and the transistor Q1 turns "ON", and the current of the constant current source I O teeth,
Load resistor R L1 switches through transistor Q1, so that the potential at the collector of transistor Q4 decreases, while the potential at the collector of transistor Q5 increases. At this time, as shown in the same figure, the emitter follower Q is connected to the collectors of transistors Q4 and Q5.
6 and Q7 are connected, and their respective emitters are set to complementary output and true value output OUT, respectively, a set state is obtained in which the true value output potential is at a high level and the complementary output potential is at a low level.
又、その後、セツト信号Ｓを再び低レベルに戻
せば、当初のデータ保持状態となり、セツト状態
のまま保持を続ける事は明らかである。 It is clear that if the set signal S is then returned to a low level, the data will be held in the original state and will continue to be held in the set state.
リセツト信号端子Ｒを高レベルにした場合は、
上記と同様に、トランジスタＱ２の電流が、トラ
ンジスタＱ３に切換わり、真値出力OUTが低レ
ベル、相補出力が高レベルのリセツト状態
に変化する。 When reset signal terminal R is set to high level,
Similarly to the above, the current of the transistor Q2 is switched to the transistor Q3, and the true value output OUT is at a low level and the complementary output is at a high level, changing to a reset state.
以上の動作に於いて、セツト，リセツト信号に
よる状態変化はトランジスタＱ１〜Ｑ３の間の電
流切換によつて行われ、このとき入力信号のしき
い値は、トランジスタＱ２のベースに供給される
基準電圧で設定されるから、セツト及びリセツト
の確度は通常のゲートと全く同一となり、従来回
路に比べて安定動作が可能である。又、構成素子
数は、トランジスタＱ２が追加されたのみで、消
費電力については、１つの定電流源のみを使用し
ているから、従来回路と全く同一である。 In the above operation, the state change due to the set and reset signals is performed by switching the current between transistors Q1 to Q3, and at this time, the threshold of the input signal is set to the reference voltage supplied to the base of transistor Q2. Since the setting and reset accuracy is exactly the same as that of a normal gate, stable operation is possible compared to the conventional circuit. Further, the number of constituent elements is only that the transistor Q2 is added, and the power consumption is exactly the same as the conventional circuit because only one constant current source is used.
尚、第２図ではNPNトランジスタを用いてい
るが、PNPトランジスタを用いても同様の効果
を得られる事は明らかである。 Although an NPN transistor is used in FIG. 2, it is clear that the same effect can be obtained by using a PNP transistor.
以上の様に本発明によれば、従来回路に僅かト
ランジスタ一個を追加するのみで、入力信号に対
するしきい値が通常ゲート回路並の安定動作をす
るセツト＝リセツト フリツプフロツプを得る事
ができる。 As described above, according to the present invention, by adding only one transistor to the conventional circuit, it is possible to obtain a set-reset flip-flop whose threshold value for input signals operates stably as that of a normal gate circuit.
第１図は従来の電流切換型論理回路を示す回路
図、第２図は本発明によるセツト＝リセツト フ
リツプフロツプの実施例を示す回路図である。
QA〜QF……トランジスタ、RL1，RL2……負荷
抵抗、IO……定電流源、Ｓ……セツト信号入力端
子、Ｒ……リセツト信号入力端子、RE1，RE2…
…エミツタフオロア抵抗、VCC……高位側電圧
源、VEE……低位側電圧源、Q1〜Q7……トランジ
スタ、VR……基準電圧源、OUT……真値出力端
子、……相補出力端子。
FIG. 1 is a circuit diagram showing a conventional current switching type logic circuit, and FIG. 2 is a circuit diagram showing an embodiment of a set-reset flip-flop according to the present invention. Q A to Q F ...Transistor, R L1 , R L2 ...Load resistance, I O ...Constant current source, S...Set signal input terminal, R...Reset signal input terminal, R E1 , R E2 ...
...Emitter follower resistance, V CC ...High-side voltage source, V EE ...Low-side voltage source, Q 1 to Q 7 ...Transistor, V R ...Reference voltage source, OUT ...True value output terminal, ...Complementary Output terminal.
Claims (1)
ンジスタと、ベースに基準電圧源が与えられる第
２のトランジスタと、ベースにリセツト信号が入
力される第３のトランジスタと、コレクタを該第
１のトランジスタのコレクタに接続し、エミツタ
を該第２のトランジスタのコレクタに接続した第
４のトランジスタと、コレクタを該第３のトラン
ジスタのコレクタおよび該第４のトランジスタの
ベースに接続し、エミツタを該第２のトランジス
タのコレクタに接続しベースを該第４のトランジ
スタのコレクタに接続した第５のトランジスタ
と、該第４のトランジスタのコレクタに接続され
る第１の負荷抵抗と、該第５のトランジスタのコ
レクタに接続される第２の負荷抵抗と、前記第
１、第２、第３のトランジスタのエミツタに接続
される定電流源と該第一のトランジスタのコレク
タに接続され相補出力を得る第一のエミツタフオ
ロアと、該第三のトランジスタのコレクタに接続
され真値出力を得る第二のエミツタフオロアとを
有することを特徴とする電流切換型セツト＝リセ
ツト フリツプフロツプ。1 A first transistor to which a set signal is input to the base, a second transistor to which a reference voltage source is applied to the base, a third transistor to which a reset signal is input to the base, and a collector connected to the first transistor. a fourth transistor having its emitter connected to the collector of the second transistor, and having its collector connected to the collector of the third transistor and the base of the fourth transistor, and having its emitter connected to the collector of the second transistor; a fifth transistor connected to the collector of the transistor and whose base is connected to the collector of the fourth transistor; a first load resistor connected to the collector of the fourth transistor; and a collector of the fifth transistor. a constant current source connected to the emitters of the first, second, and third transistors; and a first emitter follower connected to the collector of the first transistor to obtain a complementary output. and a second emitter follower connected to the collector of the third transistor to obtain a true value output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58143363A JPS6033731A (en) | 1983-08-05 | 1983-08-05 | Current switching type set-reset flip-flop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58143363A JPS6033731A (en) | 1983-08-05 | 1983-08-05 | Current switching type set-reset flip-flop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6033731A JPS6033731A (en) | 1985-02-21 |
| JPH0231528B2 true JPH0231528B2 (en) | 1990-07-13 |
Family
ID=15337039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58143363A Granted JPS6033731A (en) | 1983-08-05 | 1983-08-05 | Current switching type set-reset flip-flop |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6033731A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61144115A (en) * | 1984-12-18 | 1986-07-01 | Sony Corp | Flip-flop |
-
1983
- 1983-08-05 JP JP58143363A patent/JPS6033731A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6033731A (en) | 1985-02-21 |
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