JPS6315527A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce the discharge time of a negative noise due to incoming of the alpha-ray by connecting a constant current circuit to a resistor through which a current is supplied from a power supply connected to ground to the collector of a transistor (TR) being a component of a current switch and causing a small current to flow to the said resistor to reduce the resistance while keeping the output level constant. CONSTITUTION:TRs Q1, Q2 and Q3 constitute the current switch and the emitter current flows to the constant current circuit 20. The collector of the TR Q1 is connected to the power supply Vcc of ground level via a resistor R1, and each collector of the TRs Q2, Q3 is connected to the said power supply via a resistor R2(=R1). Further, the collector of the TR Q1 is connected to a TR Q4 of the emitter follower constitution and connected to one terminal of a constant current circuit 21, each collector of the TRs Q2, Q3 is connected to the base of a TR Q5 of emitter follower constitution and the other terminal of the constant current circuits 21, 22 is connected to a power supply terminal VEE of a negative level. The constant current circuits 21, 22 supply a smaller current i2 than the current i1 of the constant current circuit 20.

Description

[Detailed Description of the Invention] [PR Required] The present invention is a logic circuit in which a constant current circuit is connected to a resistor that supplies current from a grounded power source to the collector of a transistor constituting a current switch. By passing a small current through the J to keep the output level constant and reducing the resistance value, the discharge time of the negative polarity noise caused by the incoming alpha rays can be shortened, and the pulse width can be shortened.
Ru.

[Industrial application field]

The present invention relates to a logic circuit, and more particularly to an ECL type logic circuit installed before a flip-flop or the like.

Semiconductor integrated circuits of logic circuits have circuit configurations in which combinational circuits such as AND circuits and OR circuits and sequential circuits such as flip 70 tubes and registers are combined in various ways.

In the above logic circuit, as shown in FIG. 4, the input to the D-type flip-flop 1, which is a sequential circuit, is generally supplied through an OR circuit 2, which is a combinational circuit.

[Conventional technology]

FIG. 5 shows a circuit diagram of an example of a conventional logic circuit.11 This circuit is an ECL (emitter coupled logic) type OR circuit and is used in OR circuit 2 in FIG.

In the figure, terminal 10 or 11 is the reference voltage VRE of terminal 12.
When the torque is higher than F, almost no current flows through the resistor R1 and the transistor Q1, and a signal of 1 level is output from the terminal 13.

[Problem that the invention seeks to solve]

In the circuit shown in Fig. 5, when a signal of 1 lvl is being output from terminal 13, if α rays enter this circuit,
Resistor R, which is the collector and diffused resistance of transistor Q+
An ionization phenomenon occurs at the junction of transistor Q1, the collector potential of transistor Q1 drops instantaneously, and the output signal level of terminal 13 drops.

In other words, negative polarity noise is generated by α rays.

When the voltage at the terminal 13 falls below the threshold level of the flip-flop 1 due to the negative polarity noise, the flip-flop 70 latch 1 will latch the data input, causing a malfunction.

Furthermore, when the output signal of the circuit shown in Figure 5 is supplied to the set input terminal or reset input terminal of an SR type flip-flop, for example, the internal state of the SR type flip-flop is similarly reversed, causing malfunction. .

The present invention has been made in view of these points, and it is an object of the present invention to provide a logic circuit that shortens the discharge time of negative polarity noise due to alpha rays and shortens its pulse width.

[Means for solving problems]

The logic circuit according to the present invention includes a plurality of transistors (Ql~
Q13) is provided corresponding to each of the plurality of resistors (R+ to Rs) that supply current from the ground level power supply (Vcc), and the plurality of transistors (Q1 to Q13)
A plurality of constant current circuits (21, 22, 26, 27), one end of which is connected to the connection point between the , 41>.

[Effect]

For example, the market time T of negative polarity noise due to α rays at the collector of the transistor Q1 is determined by the junction capacitance of the collector of the transistor Q+ and the resistor R1, and the transistor Q
The sum of the stray capacitance of the collector of 1 is C, and the resistances R0 and R
Letting the sum with 1 be R, it is expressed as follows.

0cC-R In the present invention, the above-mentioned resistance R is R compared to the conventional one.

Therefore, the time T111 of the negative polarity noise becomes shorter, and its pulse width becomes shorter.

〔Example〕

FIG. 1 shows a circuit diagram of a first embodiment of a logic circuit according to the present invention. In the same figure, the same parts as in Fig. 5 are given the same reference numerals.
The explanation will be omitted.

The circuit shown in FIG. 1 is an ECL type OR circuit and a NOR circuit. Transistors Q+, Q2, and Q3 constitute an h-rent switch, and their emitter currents flow through the constant current circuit 20. The collector of transistor QI is resistor R1
The collectors of each of transistors Q2 and Q3 are connected to a resistor R.
2 (=R1) to the power supply V'cc.

Further, the collector of transistor Q+ is connected to the base of transistor Q4 having an emitter follower configuration, and
It is connected to one end of the constant current circuit 21, and the (
l! ! The end is connected to a power supply VEE at a negative level /lz (=-5, 2V). The collector of each transistor Q2.03 is a transistor Q5 with an emitter follower configuration.
is connected to the base of the constant current circuit 22 and one end of the constant current circuit 22, and the (l!! end of the constant current circuit 22 is
It is connected to the.

Each of the constant current circuits 21 and 22 flows a current 12 that is smaller than the current 11 that the constant current circuit 20 flows.

When the voltage at the terminal 10 or 11 becomes higher than the reference voltage VREF at the terminal 12, almost no current flows through the transistor QI, but current 12 flows through the resistor R1 due to the constant current circuit 21.

Since the current 12 is a small current, the output signal of the OR output of the terminal 13 connected to the emitter of the transistor Q4 is a trubel.

Further, at this time, a current i+ from the constant current circuit 20 and a current 12 from the constant current circuit 22 flow through the resistor R2, and the output signal of the NOR output j from the terminal 23 connected to the emitter of the transistor Q5 is a torque signal.

In this way, during the torque output of terminal 13, even if the α rays enter and the level of the output signal of terminal 13 decreases, the discharge time is short (4g), so the pulse width is short ( It is possible to prevent the next stage flip-flop from malfunctioning.

Similarly, when terminals 10 and 11 are trubels, even if the level of the output signal at terminal 23 decreases due to the inflow of alpha rays, the discharge time becomes shorter and the pulse width becomes shorter.

FIG. 2 shows a circuit diagram of a second embodiment of the circuit of the invention. This circuit is an ECL type AND circuit and a NAND circuit. Transistors Q6 and Qy constitute a current switch,
Each emitter is connected to a constant current circuit 24 through which current 11 flows. The transistors Qs, 09 constitute a current switch, the emitter of each is connected to the collector of the transistor Q7, the collector of each is connected to the resistor R3, RJ
It is connected to the power supply Vcc via. transistor Q
The base of transistor 2 is connected to the emitter of transistor 0+o and a constant current circuit 25 through which a small current 12 flows.

The collector of the transistor Q8 is connected to the base of the transistor Q11 having an emitter follower configuration and is also connected to the constant current source 26, and the collector of the transistor Q9 is connected to the base of the transistor Q12 having an emitter follower configuration and a constant current source 26 for flowing the light current 11. It is connected to a current source 27.

Terminal 28 is at a higher torque than the reference voltage VREFI of terminal 29, and terminal 30 is higher than the reference voltage VREFI of terminal 29.
When the torque is higher than l, almost no current flows through transistor Q8 and transistor Q6,
A small current 12 flows through the resistor R3 by a constant current circuit 25, and a terminal 32 is connected to the emitter of the transistor C)++.
The AND output signal of is the trubel. Terminal 3 like this
At the time of torque output of 2, alpha rays enter terminal 3.
Even if the level of the output signal No. 2 decreases, the discharge time becomes shorter, so the pulse width becomes shorter.

Similarly, when terminal 28 or 30 is a torque bell, α
Even if the level of the output signal at the terminal 33 decreases due to the introduction of the line, the discharge time becomes shorter and the pulse width becomes shorter.

FIG. 3 shows a circuit diagram of a third embodiment of the circuit of the invention. In this figure, the same parts as in FIG. 2 are designated by the same reference numerals, and their explanations will be omitted.

In the figure, a transistor Qa constituting a current switch
, Qs are connected to a constant current circuit 40 through which a current 11 flows. The terminal 31 has a reference ff1ff:Vne.
p+ is supplied. Moreover, the transistor Qs,
The collector of each Qa is connected to the base of a transistor Qu. The collector of the transistor Q7 is connected to ImVcc via a resistor R5, and is also connected to the base of a transistor Q+a having an emitter-follower configuration, and to a constant current circuit 41 that allows a small snow flow 12 to flow.

When the terminals 28 and 30 are at a higher torque than the reference voltage VREFI, a small current 12 flows through the resistor R3 by the constant current circuit 26, and the output C8 of the terminal 32 is at a torque higher than the reference voltage VREFI. Also, when the voltage at the terminal 28 or 30 is lower than the -voltage VRE F l, a small current 12 flows through the resistors R4 and Rs through the constant current circuit 27.41, respectively, and the output signal at the terminal 33 is at 1 - level. In this way, terminal 32 or 3
When outputting 1 level of 3, even if the level of the output signal decreases due to the input of α rays, the pulse width becomes shorter.

(Effects of the Invention) As described above, according to the present invention, it is possible to shorten the discharge time of the zero polarity noise generated by the inflow of alpha rays, and the pulse width of the level reduction of the output horn signal of the truvel can be shortened. This makes it possible to prevent malfunctions of flip-flops and the like in the subsequent stages.

[Brief explanation of drawings]

Figures 1, 2, and 3 are circuit diagrams of each embodiment of the logic circuit according to the present invention, Figure 4 is a diagram showing connections of the logic circuit, and Figure 5 is a circuit diagram of an example of a conventional circuit. It is. In the figure, 20 to 22, 24 to 27, 40, and 41 are constant current circuits, R1 to R5 are load resistors, and Q1 to Q13 are transistors. Honji 5 octopus" circuit capital

Claims (1)

[Claims] In an emitter-coupled logic type logic circuit in which a current switch is configured by a plurality of transistors (Q_1 to Q_1_3), the plurality of transistors (Q_1 to Q_1_3) are connected to an earth-level power supply (V_C_C). It is provided corresponding to each of the plurality of resistors (R_1 to R_5) that supply the current, and one end is connected to the connection point between the plurality of transistors (Q_1 to Q_1_3) and the plurality of resistors (R_1 to R_5). and a plurality of constant current circuits (21, 22, 26, 27, 41) whose other ends are connected to a negative level power supply (V_E_E)
) A logic circuit characterized by having: