JPH01151309A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify circuit constitution, to accelerate operating speed, and to improve reliability in a circuit operation by outputting logical output to execute a function in a circuit at the next stage by combining a differential circuit and a current mirror circuit. CONSTITUTION:The differential circuit 1 performs a differential operation directly answering to plural logical input A-C and reference input Vref with a prescribed voltage. And the current mirror circuit 2 performs a prescribed operation answering to a pair of output based on the differential operation. At this time, even when the fluctuation of the voltages in first or second power source lines VCC or VEE, or a difference in the performance of respective element exist, the same amount of current as that of a first transistor 22 flows on the second transistor 21 of the current mirror circuit 2. Therefore, a signal level to make the circuit 3 at the next stage execute a certain function is decided corresponding to the combination of the plural logical input A-C in spite of the fluctuation of the source voltage or the difference in the performance of the element. In such a way, it is possible to simplify the constitution of the circuit and to accelerate the operating speed, and to improve the reliability in the circuit operation.

Description

[Detailed Description of the Invention] [Summary] A semiconductor IC configured to be integrated on a semiconductor substrate and configured to perform a certain 89 functions using logic outputs output in response to a plurality of logic inputs. Regarding the device, for the purpose of reducing the number of parts, improving operating speed, and ultimately increasing the reliability of circuit operation, a first power supply line and a second power supply line with a voltage different from that of the first power supply line are connected. a group of input transistors and a reference input transistor that connect or disconnect between the first power line side and the second power line side in response to a plurality of logic inputs and a reference input of a predetermined voltage, respectively; a differential circuit that performs a differential operation based on on/off of the input transistor group and the reference input transistor; and a differential circuit connected between the differential circuit and the first or second power supply line; a first transistor that is conductive when the reference input transistor is on and causes a predetermined amount of current to flow; a first transistor that is conductive when the reference input transistor is on and causes the predetermined amount of current to flow when the input transistor group is performing the connection operation; a current mirror circuit having a second transistor through which the same amount of current flows, and is configured to cause the next stage circuit to perform a certain function using the output from the second transistor in the current mirror circuit. .

(Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and more specifically,
A semiconductor integrated circuit device (hereinafter referred to as a semiconductor integrated circuit device) is configured to be integrated on a semiconductor substrate and performs a certain function using logic outputs output in response to a plurality of logic inputs.
equipment).

[Conventional technology]

FIG. 4 shows an example of the configuration of the conventional semiconductor RC packing apparatus described above.

The device in the figure includes inverters 40A and 40B provided corresponding to a plurality of logic inputs A, B, and C, respectively.

40G, and a first circuit (node P-Q portion) 50 that performs a predetermined logic function in response to the logic output of each inverter.
and a second circuit (portion from node Q to output terminal 01JTo) that performs a predetermined logical function in response to the output of the first circuit.
It consists of 60. Note that there is a relationship of Vcc > GND > VEE between the potentials of each power supply line. Further, in the first circuit 50, a voltage Vo that can turn on the transistor 54 is applied to the base of the transistor 54. Therefore, in this state, transistor 53 is in an off state.

To briefly explain the circuit operation of the device shown in FIG. 4, first, in the inverter 40A, when a signal of "L" level (negative voltage in this case) is input as the logic input A, the transistor 41 is turned on. 43 is off, the multi-emitter transistor 44 is also off, and the transistor 45 is also off, so the potential of the node P becomes the "II" level. On the other hand, when a signal of "+1" level (positive voltage in this case) is input as logic power A, each of the above transistors performs the opposite operation, thereby causing the potential of node P to go to "L" level. Become.

Next, in the first circuit 50, a plurality of inverters 40
When any one of A, 40B, and 40G outputs an L'' level signal, the multi-emitter transistor 51 is turned on, which turns off the transistor 52, turning off the transistor 53, and as a result, the node Q The potential of is 'L' level (VEE level in this case)
becomes. Conversely, a plurality of inverters 40A, 40B
, when all 40C output aHH level signals,
Transistor 51 is turned off, which causes transistor 52 to become conductive. Therefore, a voltage Vcc of "go" level is applied to the base of the transistor 53.
2, is applied through the resistor 55 and the Zener diode 56 in the forward direction, thereby turning on the transistor 53, and as a result, the potential at the node Q becomes the "H" level (in this case, the GND level). Note that the Zener diode 56 performs a level shift action.

Next, in the second circuit 60, the potential of the node Q becomes “
When the level is "H", the base potential of the multi-emitter transistor 61 becomes "H" level, and the GND level signal passes through the Zener diode 62 in the opposite direction to the transistor 6.
3, thereby causing the transistor 6 to
3 is on, the transistor 64 is also on, the transistor 65 is off, and the transistor 66 is also off, so the output terminal 0UTo becomes a floating state. Conversely, when the potential of the node Q is at the "L" level, the base potential of the transistor 61 is at the "L" level, and the transistor 63 remains off, so the transistor 64 is off, the transistor 65 is on, and the transistor 66 is turned off. Since the output terminal 0tlTo is also turned on, current can be drawn from the output terminal 0tlTo.

Therefore, the device in FIG. 4 as a whole consists of logical manpower A, B,
When all of them become “L” level, the potential of node P becomes “H” level.
” level, the potential of node Q is “L level, output 0UTo
is at the "11" level and functions as an AND gate.

[Problem that the invention seeks to solve]

In the conventional device described above, logic outputs output in response to multiple logic inputs are used to generate a next-stage circuit (not shown).
However, since it has a complex circuit configuration that combines inverters, logic circuits with level shift functions, etc., it has the disadvantage of having a relatively large number of parts. .

In addition, since the level shift function is achieved by combining VILE (base-emitter voltage) of several stages of transistors and Zener diodes, it is not affected by fluctuations in power supply voltage or variations in the performance of each element. This results in problems such as a lack of reliability in circuit operation.

Furthermore, the change in the input signal is caused by several stages of gates (in the example of FIG. 4, the inverter part, the first circuit, the second circuit,
In other words, there is a problem in that the operation speed is relatively slow because the process goes through three stages).

The present invention was created in view of the above-mentioned problems in the conventional technology, and provides a semiconductor IC device that can reduce the number of parts, improve operating speed, and further improve reliability of circuit operation. The purpose is to

[Means for solving problems]

The problem with the above-mentioned prior art is that in response to a first power line, a second power line having a voltage different from the first power line, a plurality of logic inputs, and a reference input of a predetermined voltage, It has an input transistor group and a reference input transistor that connect or disconnect between the first power supply line side and the second power supply line side, and has a differential input transistor group based on on/off of the input transistor group and the reference input transistor. a differential circuit that operates; a first transistor that is connected between the differential circuit and the first or second power supply line and conducts when the reference input transistor is turned on to flow a predetermined amount of current; , a current mirror circuit having a second transistor that is conductive when the reference input transistor is turned on and flows the same amount of current as the predetermined amount of current when the input transistor group is performing the connection operation. This problem is solved by providing a semiconductor IC device characterized in that the output from the second transistor in the current mirror circuit is used to cause the next stage circuit to perform a certain function.

[Operation] According to the above-described configuration, the differential circuit performs differential operation directly in response to a plurality of logic inputs and a reference input of a predetermined voltage without using an inverter or a level shift circuit. It has become. The current mirror circuit performs a predetermined operation in response to the pair of outputs based on this differential operation. At this time, even if the voltage of the first or second power supply line fluctuates or there is a difference in the performance of each element, the second
The same amount of current as the current flowing through the first transistor always flows through the transistor.

Therefore, the level of the output obtained from the second transistor, that is, the level of the signal that causes the next stage circuit to execute a certain function, is always determined by multiple logic circuits, regardless of fluctuations in the power supply voltage, variations in the performance of the elements used, etc. Determined only according to the combination of input levels.

This contributes to increasing reliability in circuit operation. Furthermore, since an inverter, a level shift circuit, etc., which were required in the past, are not used, the circuit configuration is simplified, and the operating speed can be improved accordingly.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows a circuit configuration of a semiconductor IC device as an embodiment of the present invention. This device is integrated on a semiconductor substrate and has multiple logic inputs (in this example, 3
A case will be described in which the constant current output circuit 3 is used as a circuit that executes a certain function based on a logical output output in response to human power (A, B, C). Note that in the following description, a transistor refers to an NPN transistor unless otherwise specified.

First, power line Vcc (5V) and power line VEE
A resistor 6, a PNP transistor 7 (emitter/collector), a transistor 8 (collector/emitter), and a resistor 9 are connected in series between (-*main V). A predetermined voltage V2 (*
voltage ν) is applied, thereby turning on the transistor 8. Therefore, Vref is applied to the connection point (node N) between transistors 7 and 8.
, and a predetermined voltage determined by the highest level potential of the logic inputs AXB and C.

The differential circuit 1 is composed of six transistors 11 to 16 (transistors 15 and 16 are PNP type).

The bases of transistors 11, 12, 13 and 14 have logic inputs A, B, C and a reference voltage Vref, respectively.
The collectors of each transistor are commonly connected to the collector of a PNP transistor 4, and the emitter of the transistor 4 is connected via a resistor 5 to a power supply line Vcc. The emitters of transistors 11, 12, 13 are commonly connected to the emitter of PNP transistor 15, and the emitter of transistor 14 is connected to the emitter of transistor 16. The bases of transistors 15 and 16 are connected to the aforementioned node N.

Current mirror circuit 2 consists of two transistors 21°22
The bases of each transistor are connected to each other. The collector and emitter of the transistor 21 are the collector of the transistor 15 and the power supply line V, respectively.
EE, while the collector and emitter of the transistor 22 are respectively connected to the collector and base of the transistor 16 and the power supply line ν.

Reference numeral 10 denotes a transistor for the output sofa, and the base, emitter, and collector of this transistor are respectively connected to the collector of the transistor 21 and the power supply line VEE% output terminal 0tlTo.

In the constant current output circuit 3, the base of the transistor 30 is connected to the above-mentioned output terminal 0UTo, and is also connected to the emitter of the transistor 31 and the collector of the transistor 32. The collector of the transistor 31 is connected to the power supply line Vcc via a resistor 33, and a predetermined voltage V3 (**V) is applied to its base. The emitter of the transistor 32 is connected to the power line VEE through a resistor 34, and the base thereof is connected to the power line VEH through a resistor 35, as well as to the emitter of the transistor 36 and the base of the transistor 37. There is. The emitter of this transistor 37 is connected to the power supply line VEE via a resistor 38.
Its collector is connected to output terminal 011T. On the other hand, the emitter of the transistor 30 is connected to the base of the transistor 36, the collector is connected to the collector of the transistor 36, and the emitter is connected to the ground (G) via a resistor 39.
ND) has been done. Note that the transistors 32 and 37 and the resistors 34 and 38 constitute a current mirror circuit.

Next, the circuit operation of the jC device shown in FIG. 1 will be explained.

Assume now that a voltage higher than the base potential of the transistors 11, 12, and 13 is applied to the base of the transistor 14 as the reference voltage Vref. In this state, transistors 4, 14 and 16 are on, so transistors 21 and 22 in current mirror circuit 2 are both on. However, since none of the input transistors 11 to 13 are turned on, the collector potential of transistor 21 is approximately at the level of VEE, and therefore transistor 10 is in an off state. Therefore, the output terminal 0LITo is in a floating state.

Subsequently, when a logic input of level "1" is applied to any of the input transistors 11, 12, and 13, that transistor (assumed to be 11) is turned on, and thereby the resistor is connected from the high-level power supply line Vcc. 5, transistor 4,
The low power supply line vE! is connected via transistor 11, transistor 15 and transistor 21. A current flows through. This supplies current to the base of transistor 10, turning it on.

In this case, the amount of current flowing through the transistor 21 is adjusted to be the same as the amount of current flowing through the transistor 22 by the action of the current mirror circuit 2. This adjustment occurs regardless of variations in power supply voltage or differences in device performance. In other words, the base potential of the transistor 10 is always determined only according to the combination of the logic levels A and BSC, regardless of variations in power supply voltage, variations in device performance, and the like.

When the transistor 10 is turned off, the transistor 31 receives the predetermined voltage v3 and is turned on, so current is supplied to the base of the transistor 30, turning the transistor on, and a GND level voltage is applied to the base of the transistor 36. Then the transistor 36 turns on. As a result, a voltage lower by VIE than the base potential of transistor 36 is applied to each base of transistors 32 and 37, so both transistors are turned on, and the same amount of current flows through transistor 32 as the current flowing through transistor 32.
Current flows through (constant current output function).

As described above, according to the configuration shown in FIG. 1, by simply combining the differential circuit 1 and the current mirror circuit 2, a logic output for executing a certain function (in this embodiment, a constant current output function) can be output. can do. In this way, the circuit configuration is relatively simple, which improves the operating speed, and since the configuration is not affected by fluctuations in power supply voltage or variations in element performance, it improves circuit operation. reliability will increase.

FIG. 2 shows a circuit configuration of a modified example 2a of the current mirror circuit shown in FIG. The configuration upper limit in the case of FIG. A transistor 2 whose collector is grounded between
4 (emitter, base) are interposed.

In the configuration example shown in FIG. 1, the base potentials of the transistors 21 and 22 change in conjunction with the collector potential of the transistor 22. However, in the configuration example shown in FIG. 2, the collector potential of the transistor 22 is logically high.
When the transistor 24 is on, the transistor 24 is in the on state, and each base potential is stabilized at the ground level (GND level) by the resistor 23, so even if the collector potential of the transistor 22 changes slightly, the transistors 21 and 22 are on. It has the characteristic that the state is maintained stably.

In the above-described embodiment, the differential circuit 1 is placed on the side where the power supply voltage is higher (power line Vcc side), and the current mirror circuit 2 is placed on the side where the power supply voltage is lower (power line VEE side). , the arrangement relationship can also be reversed as shown in FIG.

However, in this case, it is desirable to provide a constant current source S between the power supply line VEE and the differential circuit 1.

Furthermore, in the above-described embodiment, the logic inputs A and BSC are input in parallel to the differential circuit 1, and the logic inputs A and BSC are thereby configured to function as an OR gate together with the current mirror circuit 2. may be input in series so that the whole functions as a Nands gate.

Further, in the above-described embodiments, the circuit is mainly constructed using NPN type transistors, but it is also possible to replace this with a PNP type transistor, and such a modification will be obvious to those skilled in the art.

〔Effect of the invention〕

As explained above, according to the half-circumferential IC device of the present invention,
By simplifying the configuration of the circuit that outputs a signal (logic output) to execute a certain function in response to multiple logic inputs, it is possible to reduce the number of parts and reduce the number of gates through which the signal passes. The operation speed is improved by reducing the number of times.

Further, since the circuit configuration is not affected by fluctuations in power supply voltage, variations in device performance, etc., reliability in circuit operation can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a semiconductor IC device as an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a modified example of the current mirror circuit shown in FIG. 1, and FIG. 3 is a circuit configuration diagram of a modified example of the current mirror circuit shown in FIG. FIG. 4 is a block configuration diagram of a modified example of the main part. FIG. 4 is a circuit configuration diagram of a semiconductor RC device as an example of a conventional type. (Explanation of symbols) 1... Differential circuit, 2.2a... Current mirror circuit, 3... Next stage circuit (constant current output circuit), 11 to 14, 2
1.22...Transistor, A, B, C...Logic input, Vref...Reference input, VCC, VEE...Power line. FIG. 2 is a circuit diagram of a modification of the current mirror circuit shown in FIG. 1. FIG. 3 is a block diagram of a modification of the main parts of the device.

Claims (1)

[Claims] A first power line (V_C_C), and a second power line (V_C_C) having a voltage different from that of the first power line (V_C_C).
V_E_E), multiple logic inputs (A, B, C) and a reference input of a predetermined voltage (
an input transistor group (11, 12, 13) and a reference input transistor (14) that connect or disconnect between the first power supply line side and the second power supply line side in response to Vref), respectively; a differential circuit (1) that performs differential operation based on on/off of the input transistor group and the reference input transistor; and a differential circuit (1) connected between the differential circuit and the first or second power supply line. , a first transistor (22) that is conductive when the reference input transistor is on and conducts a predetermined amount of current; and a first transistor (22) that is conductive when the reference input transistor is on and that is conductive when the input transistor group is performing the connection operation. A current mirror circuit (2, 2a) having a predetermined amount of current and a second transistor (21) that flows the same amount of current, and uses the output from the second transistor in the current mirror circuit to perform the following: A semiconductor integrated circuit device characterized in that a stage circuit (3) is made to perform a certain function.