JPH05335934A - Current mode logic circuit - Google Patents

Abstract

PURPOSE:To provide an ECL differential circuit able to be in operation at a high speed whose signal delay time is made adjustable with simple configuration. CONSTITUTION:A resistance of a collector resistor R1 in collector resistors R1, R2 being loads to a differential transistor(TR) pairs comprising TRs Q1, Q2 is selected to be smaller than a resistance of the collector resistor R2. Moreover, the resistance of the emitter resistor R5 in emitter resistors R5, R6 of the emitter follower comprising TRs Q4,Q5 is selected smaller than the resistance of the emitter resistor R6. Then an input signal A being a logic signal level (inverted input Q1, Q2. Then a logic signal amplitude of an output signal O outputted from the TRQ4 is set smaller than the level of the inverted output signal the inverse of O outputted from the TR Q5. Thus, the time when the logic signal levels of the output signals O, inverse of O are in crossing till the logic signal level of the input signal A is inverted.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to current mode logic (CML).

The CML is a CSL (current steering).
logic) or ECL (emitter coupled logic) (hereinafter referred to as ECL). ECL is
It is an emitter-coupled logic circuit that enables a high-speed operation by operating a bipolar transistor in an unsaturated region to eliminate the accumulation of carriers in the base region, and is often used in high-speed computers.

By the way, in recent years, with the increase in speed of computers, higher-speed logic circuits have been demanded. It is also required to make the signal delay time of the logic circuit adjustable and omit the signal delay circuit. Therefore, in ECL as well, it is required to be faster than before and to be able to adjust the signal delay time.

[0004]

2. Description of the Related Art FIG. 7 shows a conventional ECL circuit. The emitters of the two NPN transistors Q1 and Q2 are commonly connected to form a differential transistor pair. The resistor R1 is connected to the collector of the transistor Q1 and the transistor Q2
A resistor R2 is connected to each collector of
1, R2 are connected to the high potential side power source Vcc via a resistor R3. The emitters of the transistors Q1 and Q2 are NP
It is connected to the low-potential-side power supply VEE1 via the N-transistor Q3 and the resistor R4.

The collector of the NPN transistor Q4 is connected to the high potential side power source Vcc, and the emitter is connected to the low potential side power source VEE2 via the resistor R5. The collector of the NPN transistor Q5 is connected to the high potential side power source Vcc, and the emitter is connected to the low potential side power source VEE2 via the resistor R6.

The base of the transistor Q4 is connected to the collector of the transistor Q1 and the base of the transistor Q5 is connected to the collector of the transistor Q2. Then, the output is taken out from the emitters of the transistors Q4 and Q5. That is, each of the transistors Q4 and Q5 constitutes an emitter follower.

The resistance values of the resistors R1 and R2 are set to be equal. Further, the resistance values of the resistors R5 and R6 are also set to be equal. Further, a constant voltage VS is input to the base of the transistor Q3, and the transistor Q3 produces a constant on-resistance. That is, the on resistance of the transistor Q3 and the series resistance of the resistance R4 are
It serves as a common emitter resistance of the transistors Q1 and Q2.
The common emitter resistance is set to a large value so that the common emitter potential of each of the transistors Q1 and Q2 is set to be constant when any of the transistors Q1 and Q2 of the differential transistor pair is turned on.

Then, the reference voltage Vr is input to the base of the transistor Q2, and the input signal A is input to the base of the transistor Q1. Then, the input signal A from the reference voltage Vr
When the potential of is high enough (when the input signal A is at H level), the transistor Q1 is turned on and the transistor Q2 is turned off. Then, a collector current flows through the transistor Q1, and the collector potential of the transistor Q1 (base potential of the transistor Q4) decreases due to the voltage drop across the resistors R3 and R1, turning off the transistor Q4. Therefore, the emitter potential of the transistor Q4 becomes L level.

On the other hand, the collector current does not flow in the transistor Q2, and only a voltage drop occurs due to the resistor R3.
Since the voltage drop due to 2 does not occur, the collector potential of the transistor Q2 (base potential of the transistor Q5) does not drop and the transistor Q5 turns on. Therefore, the emitter potential of the transistor Q5 becomes H level.

On the contrary, the reference voltage V
When r is sufficiently high (when input signal A is at L level)
, The emitter potential of the transistor Q4 becomes H level and the emitter potential of the transistor Q5 becomes L level.

As described above, the emitter potentials of the transistors Q4 and Q5 are at inverted levels. Therefore, the output O is taken out from the emitter of the transistor Q4, and the inverted output bar O is taken out from the emitter of the transistor Q5.

In FIG. 8, the circuit shown in FIG. 7 is connected to the transistor Q1 and an NPN transistor Q6 having a common collector and emitter, and the input signal B is input to the base of the transistor Q6. It is an example of configuring a B OR or NOR circuit.

That is, when the potential of one of the input signals A and B is sufficiently higher than the reference voltage Vr (when one of the input signals A and B is at the H level), the output O
Becomes L level, and the inverted output bar O becomes H level.
On the contrary, when the potentials of both input signals A and B are sufficiently lower than the reference voltage Vr (when both input signals A and B are L level), the output O becomes H level and the inverted output bar O becomes L level. become.

Therefore, the H level and L of the input logic signal
When the level value is determined by the reference voltage Vr (a level sufficiently higher than the reference voltage Vr is H and a sufficiently low level is L [more accurately, a base voltage for turning off the transistor Q2 (a voltage slightly higher than the reference voltage Vr). A higher voltage is an H level, a base voltage (a voltage slightly lower than the reference voltage Vr) for turning on a transistor is an L level], an output O is a NOR logic of input signals A and B, and an inverted output bar O is It becomes the OR logic of the input signals A and B.

In the ECL constructed in this manner, the voltage of the high potential side power supply VCC and the voltage of the low potential side power supplies VEE1 and VEE2 are set so that no saturation occurs when any of the transistors Q1, Q2, Q4 to Q6 is turned on. Circuit constant, input signal A, B
, And the reference voltage Vr.

That is, the ECL is each transistor Q1,
Since the transistors Q2, Q4 to Q6 are not driven to the saturation region, they belong to the unsaturated logic circuit, and each of the transistors Q1, Q
Since no carriers are accumulated in the base regions of 2, Q4 to Q6, high speed operation becomes possible.

[0017]

However, with the increase in speed of computers, there has been a demand for a logic circuit that operates at a higher speed than the conventional ECL.

Therefore, a method (called an ECL differential circuit) using an inverted input signal A or B in which the levels of the input signals A and B are inverted instead of the reference voltage Vr has been considered.

In the ECL differential circuit, on / off switching of each of the transistors Q1 and Q2 is performed by the input signals A and B and the inverted input signals A and B whose levels are relatively inverted. Therefore, the reference voltage Vr
The ECL differential circuit can operate at a higher speed than the conventional ECL in which the transistors Q1 and Q2 are switched on and off depending on whether they are sufficiently higher or sufficiently lower.

In FIG. 9, the input signal A in FIG.
FIG. 7 is an operation timing chart showing an output O and an inverted output bar O when the level is switched to H (the inverted input signal bar A is H → L).

On the other hand, FIG. 10 shows the operation timings of the output O and the inverted output bar O when the level of the input signal A is changed from H to L (the inverted input signal bar A is from L to H) in FIG. It is a figure. 9 and 10, E
The time required for the operation of the CL differential circuit is expressed as a time t1 until the output O and the inverted output bar O intersect.

However, in recent years, there has been a demand for a high speed computer, which requires a logic circuit which operates at a higher speed than the ECL differential circuit. Further, in the logic circuit, it is required not only to operate at high speed but also to be able to adjust the time required for operation (that is, signal delay time). This is because by appropriately adjusting the signal delay time in each logic circuit, the signal delay circuit conventionally provided separately from the logic circuit can be omitted.

The present invention has been made in order to satisfy the above-mentioned requirements, and an object of the present invention is to provide an ECL differential circuit which can operate at high speed and can adjust a signal delay time with a simple structure. It is to be provided by the configuration.

[0024]

[Means for Solving the Problems]
It consists of two transistors whose emitters are commonly connected.

Each collector resistor is connected between the collector of each transistor of the differential transistor pair and the high potential side power source. The respective transistors forming the emitter followers take out respective output signals of a predetermined logic signal level and logic signal amplitude from the collectors of the respective transistors of the differential transistor pair.

Each of the emitter resistors (R5, R6) is connected between the emitter of each transistor constituting the emitter follower and the low potential side power source. Then, an input signal whose logic signal level is inverted is input to the bases of the respective transistors of the differential transistor pair.

The resistance value of one of the collector resistances is set to be smaller than the resistance value of the other collector resistance. Further, the resistance value of the emitter resistance forming the emitter follower connected to the one collector resistance is set to be smaller than the resistance value of the other emitter resistance.

[0028]

Therefore, according to the present invention, the logical signal amplitude of the output signal output from the emitter follower having the smaller resistance value of the collector resistance and the emitter resistance is smaller than the logical signal amplitude of the other output signal. ..

Therefore, the time from the inversion of the logic signal level of the input signal to the crossing of the logic signal levels of the output signals, that is, the time required to perform the logic operation (the signal delay time of the logic circuit) is Can be shortened.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment embodying the present invention will now be described with reference to FIG.
Follow the instructions below. 1 is different from the conventional example shown in FIG. 7 only in that the resistance value of the resistor R1 is smaller than that of the resistor R2 and the resistance value of the resistor R5 is smaller than that of the resistor R6. 1 and 7 are the same for all other configurations, the same reference numerals are given and their description is omitted.

By making the resistance value of the resistor R1 smaller than that of the resistor R2, the L level potential of the output O becomes higher than the L level potential of the inverted output bar O. That is, as described above, when the input signal A is at H level, the transistor Q
1 is turned on, a collector current flows through the transistor Q1, and the collector potential of the transistor Q1 (transistor Q1
4), the transistor Q4 is turned off, and the output O becomes L level.

Here, the collector potential of the transistor Q1 is a value obtained by subtracting the sum (VR3 + VR1) of the voltage drop VR3 due to the resistor R3 and the voltage drop VR1 due to the resistor R1 from the voltage VCC of the high potential side power source VCC (VCC-VR3--). VR1).
Further, the emitter potential of the transistor Q4, that is, the output O
Is calculated from the collector potential (VCC-VR3-VR1) of the transistor Q1 as shown in the equation (1).
The value is the value obtained by subtracting the base-emitter voltage drop VBE of.

O = VCC-VR3-VR1-VBE (1) By the way, if the collector current of the transistor Q1 is constant, the voltage drop VR1 due to the resistor R1 becomes smaller as the resistance value of the resistor R1 becomes smaller. Therefore, when the resistance value of the resistor R1 is reduced, the voltage drop VR1 is reduced, and the emitter potential of the transistor Q4, that is, the output O is increased as shown in the equation (1).

That is, by decreasing the resistance value of the resistor R1, the L level potential of the output O increases. Here, the fact that the resistance value of the resistor R1 is smaller than that of the resistor R2 means that the resistance value of the resistor R2 is larger than that of the resistor R1. It becomes lower than the electric potential.

Since the resistance value of the resistor R5 is smaller than that of the resistor R6, the H level potential of the output O becomes lower than the H level potential of the inverted output bar O. That is,
Contrary to the above, when the input signal A is at L level, the transistor Q1 is turned off, the collector current does not flow in the transistor Q1, the collector potential of the transistor Q1 (base potential of the transistor Q4) does not decrease, and the transistor Q4
Turns on, collector current flows through the transistor Q4, and the output O becomes H level.

Here, the emitter potential of the transistor Q4, that is, the output O, is a value (VEE2 + VR) obtained by adding the voltage drop VR5 due to the resistor R5 to the voltage VEE2 of the low potential side power source VEE2.
5).

By the way, the voltage drop VR5 due to the resistor R5
If the collector current of the transistor Q4 is constant,
The smaller the resistance value of the resistor R5, the smaller the resistance value. Therefore, if the resistance value of the resistor R5 is reduced, the voltage drop VR5 is reduced, and the emitter potential of the transistor Q4, that is, the output O
(VEE2 + VR5) becomes smaller.

That is, by reducing the resistance value of the resistor R5, the H level potential of the output O becomes low. Here, the fact that the resistance value of the resistor R5 is smaller than that of the resistor R6 means that the resistance value of the resistor R6 is made larger than that of the resistor R5. Therefore, the H level potential of the inverting output bar O is equal to that of the output O level. It becomes higher than the electric potential.

In this way, when the H level potential is compared, the inverted output bar O becomes higher than the output O, and when the L level potential is compared, the output O becomes higher than the inverted output bar O. That is, the logic signal amplitude (difference between the H level and the L level) of the output O becomes smaller by the amount of the smaller resistance value of each of the resistors R1 and R5. On the other hand, since the resistance value of each of the resistors R2 and R6 is the same as that of the conventional example, the logic signal amplitude of the inverted output bar O remains the same as that of the conventional example. Then, compared with the conventional example in which the logical signal amplitudes of the output O and the inverted output bar O are the same,
The operation of the present embodiment can be sped up by the reduction of the amplitude of the logic signal of the output O.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, three first embodiments shown in FIG. 1 are connected in series. However, the resistors R of the circuits 21, 22, and 23 of each stage are
The resistance value of 1 is halved of the resistance R2, and each resistance R5
Has a resistance value half that of the resistor R6. As a result, the logical signal amplitude of the output O of the circuits 21, 22, and 23 of each stage becomes half the logical signal amplitude of the inverted output bar O. As described above, by arranging three identical circuits 21, 22, and 23 in series, it becomes clearer that the operation has been speeded up.

FIG. 4 shows the output O and the inverted output bar O of the conventional example shown in FIG. 9 when the level of the input signal A changes from L to H (the inverted input signal bar A changes from H to L).
4 is an operation timing chart in which the output On and the inverted output bar On of the second embodiment shown in FIG.

On the other hand, FIG. 5 shows the input signal A in FIG.
Is H → L (the inverted input signal bar A is L → H), the output O of the conventional example shown in FIG.
FIG. 4 is an operation timing chart in which an inverted output bar O, an output On and an inverted output bar On of the second embodiment shown in FIG.

In FIGS. 4 and 5, the logic signal amplitude of the output On is about half the logic signal amplitude of the inverted output bar On and the outputs O and the inverted output bar O. The time required for the operation of the present embodiment is represented as the time t2 until the output On and the inverted output bar On intersect, as in the conventional example. Therefore, as shown in FIGS. 4 and 5, the time t2 required for the operation of the present embodiment is smaller than the time t1 required for the operation of the conventional example, and the present embodiment is faster than the conventional example. Recognize.

In the present invention, the resistance value of each of the resistors R1 and R5 may be any value as long as it is within the saturated state no matter which of the transistors Q1, Q2 and Q4 to Q6 is turned on.

The smaller the resistance value of each of the resistors R1 and R5 is within the range, the faster the operation can be performed (however, practically, as shown in the second embodiment, each resistor is reduced. When the resistance values of R1 and R5 are set to half of the resistances of R2 and R6, respectively, various conditions can be satisfied and the highest speed can be achieved.

Therefore, by properly adjusting the resistance values of the resistors R1 and R5, the time required for the operation (that is,
Signal delay time) can be adjusted. By the way, when the present embodiment is embodied as a semiconductor integrated circuit, each resistor R
It may be constituted by a plurality of resistors having different resistance values in which 1 and R5 are connected in parallel. Then, the resistors R1 and R are provided as required by laser trimming or switching of wiring layers.
The resistance value of 5 may be changed.

FIG. 2 shows a third embodiment of the present invention. In the present embodiment, similarly to the conventional example shown in FIG. 8, the NPN transistor Q6 is connected, the input signal B is input to the base thereof, and the resistance values of the resistors R1 and R5 are set similarly to the first embodiment. They are smaller than the resistors R2 and R6, respectively.

Also in this embodiment, as in the first embodiment,
As the operation becomes faster, the logic signal amplitude of the output O becomes smaller than that of the conventional example. When the logic signal amplitude decreases, the noise margin for noise due to fluctuations in the power supply voltage and noise from the outside decreases.

Therefore, the noise margin of the output O is smaller than that of the conventional example. Therefore, using the output O of this embodiment as the NOR logic of the input signals A and B is disadvantageous because the noise margin is small.

On the other hand, since the logic signal amplitude of the inverted output bar O of this embodiment is the same as that of the conventional example, even if the inverted output bar O of this embodiment is used as the OR logic of the input signals A and B, the noise margin is small. Same as the conventional example.

Therefore, this embodiment can be used as an OR circuit capable of high speed operation. Further, in the present embodiment, contrary to the first embodiment, the resistance values of the resistors R1 and R5 are the same as those of the conventional example, and the resistance values of the resistors R2 and R6 are made larger than the resistances R1 and R5, respectively. Can also be considered.

In this case, the operation becomes faster and, contrary to the above, the logic signal amplitude of the inverted output bar O becomes smaller than that of the conventional example. Therefore, the noise margin of the inverted output bar O becomes smaller than that of the conventional example, and it is disadvantageous to use the inverted output bar O as the OR logic of the input signals A and B.

On the other hand, since the logic signal amplitude of the output O is the same as that of the conventional example, even if the output O is used as the NOR logic of the input signals A and B, the noise margin is the same as that of the conventional example. Therefore, in this case, it can be used as a NOR circuit capable of high-speed operation.

FIG. 6 shows a fourth embodiment of the present invention. In this embodiment, two first embodiments shown in FIG. 1 are connected in series. However, the output O of the circuit 31 of the previous stage and the inverted output bar O intersect and are input to the circuit 32 of the next stage. That is, the output O of the circuit 31 of the previous stage becomes the input signal B of the circuit 32 of the next stage, and the inverted output bar O of the circuit 31 of the previous stage becomes the input signal A of the circuit 32 of the next stage. In this embodiment, it can be operated as a series circuit of an OR circuit and a NOR circuit.

The present invention is not limited to the above-mentioned embodiments. For example, the resistor R3 may be omitted and the resistors R1 and R1 may be omitted.
R2 may be directly connected to the high potential side power supply Vcc. Also,
Omitting the transistor Q3, each transistor Q1, Q2
The emitter of may be directly connected to the low potential side power source VEE1.

Further, each low potential side power source VEE1, VEE2 is set to 1
It may be replaced with two low-potential-side power supplies.

[0057]

As described above in detail, according to the present invention, it is possible to provide an ECL differential circuit capable of operating at high speed and having an adjustable signal delay time with a simple structure. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment embodying the present invention.

FIG. 2 is a circuit diagram of a third embodiment.

FIG. 3 is a circuit diagram of a second embodiment.

FIG. 4 is a characteristic diagram showing the operation timing of the second embodiment.

FIG. 5 is a characteristic diagram showing the operation timing of the second embodiment.

FIG. 6 is a circuit diagram of a fourth embodiment.

FIG. 7 is a circuit diagram of a conventional ECL.

FIG. 8 is a circuit diagram of a conventional ECL differential circuit.

FIG. 9 is a characteristic diagram showing operation timing of a conventional ECL differential circuit.

FIG. 10 is a characteristic diagram showing operation timing of a conventional ECL differential circuit.

[Explanation of symbols]

 Q1 to Q6 NPN transistor R1, R2 collector resistance R5, R6 emitter resistance O output signal bar O inverted output signal A input signal bar A inverted input signal

Claims (1)

[Claims] 1. A differential transistor pair composed of two transistors (Q1, Q2) whose emitters are commonly connected, and respective transistors (Q1, Q2) of the differential transistor pair.
2) collector resistors (R1, R2) connected between the collector and the high-potential-side power source (VCC), and transistors (Q1, Q2) of the differential transistor pair.
Transistors (Q4, Q5) forming an emitter follower for taking out an output signal (O, bar O) having a predetermined logic signal level and logic signal amplitude from the collector of 2), and each transistor (Q forming the emitter follower).
4, Q5) emitters and low-potential-side power supplies (VEE2), each emitter resistance (R5, R6)
And a current input to the bases of the transistors (Q1, Q2) of the differential transistor pair, the input signals (A, A) of which the logic signal levels are inverted.
In the mode logic circuit, the resistance value of one of the collector resistors (R1, R2) is set to the resistance value of the other collector resistor (R1).
The resistance value of the emitter resistance (R5), which constitutes the emitter follower connected to the one collector resistance (R1), should be smaller than the resistance value of the other emitter resistance (R6). Current mode logic circuit characterized by.