JPH0312487B2 - - Google Patents
Info
- Publication number
- JPH0312487B2 JPH0312487B2 JP10505282A JP10505282A JPH0312487B2 JP H0312487 B2 JPH0312487 B2 JP H0312487B2 JP 10505282 A JP10505282 A JP 10505282A JP 10505282 A JP10505282 A JP 10505282A JP H0312487 B2 JPH0312487 B2 JP H0312487B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transistor
- terminal
- output
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 4
- 235000012907 honey Nutrition 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/603—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with coupled emitters
Description
【発明の詳細な説明】
この発明は、信号切換装置に関するものであ
る。第１図は従来の信号切換装置を示す回路図で
あり、１ａ，１ｂは第１、第２のトランジスタ、
２ａ，２ｂはエミツタ帰還抵抗器、３は第１の電
流源、４は負荷抵抗器であり、以上で差動増幅回
路５を構成する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal switching device. FIG. 1 is a circuit diagram showing a conventional signal switching device, in which 1a and 1b are first and second transistors,
2a and 2b are emitter feedback resistors, 3 is a first current source, and 4 is a load resistor, and the above constitutes a differential amplifier circuit 5.
６ａ，６ｂはバイアス抵抗器、７は第１の信号
入力端子、８は固定バイアス電圧供給端子、９は
第１の電源電圧供給端子である。また、１０ａ，
１０ｂは第３、第４のトランジスタ、１１は第２
の電流源であり、これらで信号切換回路を構成す
る。１２は第２の信号入力端子、１３は出力端
子、１４は第２の電源電圧供給端子である。 6a and 6b are bias resistors, 7 is a first signal input terminal, 8 is a fixed bias voltage supply terminal, and 9 is a first power supply voltage supply terminal. Also, 10a,
10b is the third and fourth transistor, 11 is the second transistor
These current sources constitute a signal switching circuit. 12 is a second signal input terminal, 13 is an output terminal, and 14 is a second power supply voltage supply terminal.
次に第１図の従来の信号切換装置の動作につい
て説明する。第１の信号入力端子７に加えられる
信号を信号S1、第２の信号入力端子１２に加えら
れる信号を信号S2とする。この装置においては、
第１の電源電圧供給端子９には常時電源電圧が印
加され、第１の信号入力端子７には信号S1が常時
加えられている。また、第２の電源電圧供給端子
１４には電源電圧が印加される時と印加されない
時とがあり、電源電圧が印加される時には第２の
信号入力端子１２に信号S2が加えられるが、電源
電圧が引加されない時には第２の信号入力端子１
２には信号S2が加えられず、第２の信号入力端子
１２は接地電位になつている。そして、第２の信
号入力端子１２に信号S2が加えられている時に
は、第４のトランジスタ１０ｂのベースにおける
信号S2の最低電位は第３のトランジスタ１０ａの
ベースに出力されている信号S1の最高電位よりも
必ず高くなるように構成されている。そのため、
第２の電源電圧供給端子１４に電源電圧が印加さ
れていない時には、第３のトランジスタ１０ａの
ベース電位の方が第４のトランジスタ１０ｂのベ
ース電位よりも必ず高いため出力端子１３に信号
S1が出力され、（以下、信号S1出力時を呼ぶこと
にする）、第２の電源電圧供給端子１４に電源電
圧が印加されている時には、第４のトランジスタ
１０ｂのベース電位の方が第３のトランジスタ１
０ａのベース電位よりも必ず高いため出力端子１
３に信号S2が出力される（以下、信号S2出力時と
呼ぶことにする）。 Next, the operation of the conventional signal switching device shown in FIG. 1 will be explained. The signal applied to the first signal input terminal 7 is referred to as a signal S 1 , and the signal applied to the second signal input terminal 12 is referred to as a signal S 2 . In this device,
A power supply voltage is always applied to the first power supply voltage supply terminal 9, and a signal S1 is always applied to the first signal input terminal 7. In addition, there are times when the power supply voltage is applied to the second power supply voltage supply terminal 14 and times when it is not applied, and when the power supply voltage is applied, the signal S 2 is applied to the second signal input terminal 12. When no power supply voltage is applied, the second signal input terminal 1
No signal S 2 is applied to the terminal 2, and the second signal input terminal 12 is at ground potential. When the signal S 2 is applied to the second signal input terminal 12, the lowest potential of the signal S 2 at the base of the fourth transistor 10b is equal to the signal S 1 output to the base of the third transistor 10a . It is configured so that the potential is always higher than the highest potential of . Therefore,
When no power supply voltage is applied to the second power supply voltage supply terminal 14, the base potential of the third transistor 10a is always higher than the base potential of the fourth transistor 10b.
When signal S 1 is output (hereinafter referred to as the time when signal S 1 is output) and the power supply voltage is applied to the second power supply voltage supply terminal 14, the base potential of the fourth transistor 10b is higher than the base potential of the fourth transistor 10b. third transistor 1
Since it is always higher than the base potential of 0a, output terminal 1
3, the signal S 2 is output (hereinafter referred to as signal S 2 output time).
以上のように、この装置においては、第２の電
源電圧供給端子１４に電源電圧を印加するかしな
いかにより出力端子１３に現われる信号が切り換
えられるのであるが、信号S2出力時には第４のト
ランジスタ１０ｂのベースにおける信号S2の最低
電位は第３のトランジスタ１０ａのベースに出力
されている信号S1の最高電位よりも必ず高くなけ
ればならないという条件があるため、差動増幅回
路５の出力ダイナミツクレンジが制限されてしま
うという欠点がある。 As described above, in this device, the signal appearing at the output terminal 13 is switched depending on whether or not the power supply voltage is applied to the second power supply voltage supply terminal 14. When the signal S2 is output, the signal appearing at the output terminal 13 is switched. Since there is a condition that the lowest potential of the signal S2 at the base of the third transistor 10b must be higher than the highest potential of the signal S1 outputted to the base of the third transistor 10a, the output dielectric of the differential amplifier circuit 5 The disadvantage is that the honey cleansing is limited.
この発明は、上記のような従来の信号切換装置
の欠点を除去するためになされたものであり、差
動増幅回路の出力ダイナミツクレンジが第４のト
ランジスタのベースにおける信号の最低電位によ
つて制限されるのを軽減するような信号切換装置
を提供することを目的としている。以下、この発
明について説明する。 This invention was made to eliminate the drawbacks of the conventional signal switching device as described above, and the output dynamic range of the differential amplifier circuit is determined by the lowest potential of the signal at the base of the fourth transistor. It is an object of the present invention to provide a signal switching device that alleviates the limitations. This invention will be explained below.
第２図はこの発明の一実施例を示すものであ
る。この図において、１５は前記第１、第２のト
ランジスタ１ａ，１ｂと共に差動的に動作する第
５のトランジスタ、１６は差動増幅回路制御端子
であり、その他は第１図と同じである。 FIG. 2 shows an embodiment of the present invention. In this figure, 15 is a fifth transistor that operates differentially together with the first and second transistors 1a and 1b, 16 is a differential amplifier circuit control terminal, and the rest is the same as in FIG. 1.
次にこの実施例の動作について説明する。差動
増幅回路制御端子１６に印加される電位は、第２
の電源電圧供給端子１４に電源電圧が印加される
時と印加されない時とで変わり、電源電圧が印加
される時には第１の電流源３の電流の一部または
全部が第５のトランジスタ１５を流れるような電
位が与えられ、一方、電源電圧が印加されない時
には第５のトランジスタ１５の第１、第２のトラ
ンジスタ１ａ，１ｂに対して十分カツトオフする
ような電位が与えられる。第３図に差動増幅回路
制御端子１６に印加する制御電圧を作成する回路
の一例を示す。１７は制御端子で、第２の電源電
圧供給端子１４に接続し、１８は制御出力端子
で、差動増幅回路制御端子１６に接続する。抵抗
器１９ａ，１９ｂは、制御端子１７の印加電圧を
分圧し、制御端子１７に電源電圧が印加された
時、上記分圧電圧が第１の電流源３の電流の全部
または一部が第５のトランジスタ１５に流れるよ
うなトランジスタ１５のベース電圧となるよう
に、その値を選んでおく。制御端子１７に電源電
圧が印加されない時は、制御出力端子１８はほぼ
接地電位となり、第５のトランジスタ１５はカツ
トオフする。この実施例の出力端子１３に出力さ
れる信号を切り換える方法は従来装置と同様であ
る。すなわち、第２の電源電圧供給端子１４に電
源電圧が印加されていない時には出力端子１３に
信号S1が出力され、第２の電源電圧供給端子１４
に電源電圧が印加されている時は出力端子１３に
信号S2が出力される。そして、信号S1出力時は第
５のトランジスタ１５がカツトオフしているた
め、従来装置と動作は全く同一である。一方、信
号S2出力時は第１の電流源３の電流の一部または
全部が第５のトランジスタ１５を通して流れるた
め、従来装置と比べて第５のトランジスタ１５を
通して流れる電流による負荷抵抗器４の電圧降下
分だけ第３のトランジスタ１０ａのベースの最高
電位が低くなる。従つて、その分だけ差動増幅回
路５の出力ダイナミツクレンジを広くすることが
できる。 Next, the operation of this embodiment will be explained. The potential applied to the differential amplifier circuit control terminal 16 is
It changes depending on when the power supply voltage is applied to the power supply voltage supply terminal 14 of the power supply voltage supply terminal 14 and when it is not applied, and when the power supply voltage is applied, part or all of the current of the first current source 3 flows through the fifth transistor 15. On the other hand, when the power supply voltage is not applied, a potential is applied to the first and second transistors 1a and 1b of the fifth transistor 15 such that they are sufficiently cut off. FIG. 3 shows an example of a circuit for creating a control voltage to be applied to the differential amplifier circuit control terminal 16. 17 is a control terminal connected to the second power supply voltage supply terminal 14, and 18 is a control output terminal connected to the differential amplifier circuit control terminal 16. The resistors 19a and 19b divide the voltage applied to the control terminal 17, and when the power supply voltage is applied to the control terminal 17, the divided voltage is such that all or part of the current of the first current source 3 is The value is selected so that the base voltage of the transistor 15 flows through the transistor 15. When no power supply voltage is applied to the control terminal 17, the control output terminal 18 is approximately at ground potential, and the fifth transistor 15 is cut off. The method of switching the signal output to the output terminal 13 in this embodiment is the same as in the conventional device. That is, when the power supply voltage is not applied to the second power supply voltage supply terminal 14, the signal S1 is output to the output terminal 13, and the second power supply voltage supply terminal 14
When the power supply voltage is applied to the output terminal 13, the signal S2 is outputted to the output terminal 13. Since the fifth transistor 15 is cut off when the signal S1 is output, the operation is exactly the same as that of the conventional device. On the other hand, when the signal S 2 is output, part or all of the current from the first current source 3 flows through the fifth transistor 15, so compared to the conventional device, the current flowing through the fifth transistor 15 increases the load resistor 4. The highest potential at the base of the third transistor 10a is lowered by the voltage drop. Therefore, the output dynamic range of the differential amplifier circuit 5 can be widened by that much.
なお、上記の説明においては、第１の信号入力
端子７に常時信号S1が加えられているとしたが、
信号S2出力時に信号S1が加えられていなくても同
様の効果があり、また、信号S1出力時には第４の
トランジスタ１０ｂのベース電位は接地電位にな
つているとしたが、接地電位になつていなくて
も、第３のトランジスタ１０ａのベースの最低電
位よりも低い電位であれば同様の効果がある。ま
た、上記の実施例で用いた各トランジスタは
NPNトランジスタであつたが、この代わりに
PNPトランジスタ等の素子を用いることもでき
ることは言うまでもない。 Note that in the above explanation, it is assumed that the signal S1 is constantly applied to the first signal input terminal 7;
The same effect can be obtained even if the signal S 1 is not applied when the signal S 2 is output, and it is assumed that the base potential of the fourth transistor 10b is at the ground potential when the signal S 1 is output. Even if the potential is lower than the lowest potential of the base of the third transistor 10a, the same effect can be obtained. In addition, each transistor used in the above example is
It used to be an NPN transistor, but instead of this
It goes without saying that elements such as PNP transistors can also be used.
以上詳細に説明したように、この発明の信号切
換装置によれば、第４のトランジスタの信号の出
力時に第１の電流源の電流の一部または全部を第
５のトランジスタを通して流してやることによ
り、差動増幅回路の出力ダイナミツクレンジが、
第４のトランジスタの信号出力時の第４のトラン
ジスタのベースにおける信号の最低電位により制
限されるのを軽減することができ、条件によつて
は全く制限されないようにすることが可能にな
る。また、差動増幅回路制御端子に印加する電位
は、第２の電源電圧供給端子に印加される電圧を
抵抗分割すること等により作ることができ、素子
数の増加も少ない等の利点がある。 As explained in detail above, according to the signal switching device of the present invention, by causing part or all of the current of the first current source to flow through the fifth transistor when the signal of the fourth transistor is output, The output dynamics range of the differential amplifier circuit is
It is possible to reduce the limitation caused by the lowest potential of the signal at the base of the fourth transistor when the signal is output from the fourth transistor, and it becomes possible to eliminate the limitation at all depending on the conditions. Further, the potential applied to the differential amplifier circuit control terminal can be created by resistively dividing the voltage applied to the second power supply voltage supply terminal, etc., and there are advantages such as a small increase in the number of elements.
第１図は従来の信号切換装置を示す回路図、第
２図はこの発明の一実施例を示す回路図、第３図
は制御電圧を作成する手段を説明するための回路
図である。
図中、１ａ，１ｂは第１、第２のトランジス
タ、３は第１の電流源、４は負荷抵抗器、５は差
動増幅回路、７は第１の信号入力端子、１０ａ，
１０ｂは第３、第４のトランジスタ、１１は第２
の電流源、１２は第２の信号入力端子、１３は出
力端子、１５は第５のトランジスタ、１６は差動
増幅回路制御端子である。なお、図中の同一符号
は同一または相当部分を示す。
FIG. 1 is a circuit diagram showing a conventional signal switching device, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram for explaining means for creating a control voltage. In the figure, 1a and 1b are first and second transistors, 3 is a first current source, 4 is a load resistor, 5 is a differential amplifier circuit, 7 is a first signal input terminal, 10a,
10b is the third and fourth transistor, 11 is the second transistor
12 is a second signal input terminal, 13 is an output terminal, 15 is a fifth transistor, and 16 is a differential amplifier circuit control terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
スタ、および第１の電流源、および負荷抵抗器と
からなる差動増回路と；ベースに前記差動増幅回
路の出力が加えられている第３のトランジスタ
と、エミツタが前記第３のトランジスタのエミツ
タと第２の電流源と出力端子に接続され、ベース
が第２の信号入力端子となつている第４のトラン
ジスタと、エミツタが前記第１の電流源に接続さ
れ、コレクタが前記負荷抵抗器に接続された第５
のトランジスタを備え；前記第１の信号入力端子
の入力信号を前記出力端子より出力する時は、前
記第２の信号入力端子に前記第３のトランジスタ
のベース電位よりも低い電位を印加し、前記第２
の信号入力端子の入力信号を前記出力信号より出
力する時は、前記第１の電流源の電流の一部もし
くは全部が前記第５のトランジスタのコレクタ電
流として流れるようなベース印加電位を前記第５
のトランジスタのベースに印加することを特報と
する信号切換装置。1 A differential amplifier circuit consisting of a first signal input terminal, first and second transistors, a first current source, and a load resistor; the output of the differential amplifier circuit is added to the base. a third transistor, a fourth transistor whose emitter is connected to the emitter of the third transistor, the second current source and the output terminal, and whose base is a second signal input terminal; a fifth current source connected to the first current source and having a collector connected to the load resistor;
a transistor; when outputting the input signal of the first signal input terminal from the output terminal, a potential lower than the base potential of the third transistor is applied to the second signal input terminal; Second
When outputting the input signal of the signal input terminal from the output signal, the potential applied to the base of the fifth transistor is such that part or all of the current of the first current source flows as the collector current of the fifth transistor.
A signal switching device whose special signal is applied to the base of a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10505282A JPS58220524A (en) | 1982-06-16 | 1982-06-16 | Signal switching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10505282A JPS58220524A (en) | 1982-06-16 | 1982-06-16 | Signal switching device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58220524A JPS58220524A (en) | 1983-12-22 |
| JPH0312487B2 true JPH0312487B2 (en) | 1991-02-20 |
Family
ID=14397211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10505282A Granted JPS58220524A (en) | 1982-06-16 | 1982-06-16 | Signal switching device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58220524A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102208688B1 (en) * | 2020-07-23 | 2021-01-28 | 주식회사 어반베이스 | Apparatus and method for developing object analysis model based on data augmentation |
| KR102234609B1 (en) * | 2020-07-23 | 2021-04-02 | 주식회사 어반베이스 | Apparatus and method for recommending goods based on analysis of image database |
-
1982
- 1982-06-16 JP JP10505282A patent/JPS58220524A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102208688B1 (en) * | 2020-07-23 | 2021-01-28 | 주식회사 어반베이스 | Apparatus and method for developing object analysis model based on data augmentation |
| KR102234609B1 (en) * | 2020-07-23 | 2021-04-02 | 주식회사 어반베이스 | Apparatus and method for recommending goods based on analysis of image database |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58220524A (en) | 1983-12-22 |
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