JPH0145766B2 - - Google Patents

Info

Publication number
JPH0145766B2
JPH0145766B2 JP57064372A JP6437282A JPH0145766B2 JP H0145766 B2 JPH0145766 B2 JP H0145766B2 JP 57064372 A JP57064372 A JP 57064372A JP 6437282 A JP6437282 A JP 6437282A JP H0145766 B2 JPH0145766 B2 JP H0145766B2
Authority
JP
Japan
Prior art keywords
transistor
collector
transistors
gain control
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57064372A
Other languages
Japanese (ja)
Other versions
JPS58181310A (en
Inventor
Yasunori Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6437282A priority Critical patent/JPS58181310A/en
Publication of JPS58181310A publication Critical patent/JPS58181310A/en
Publication of JPH0145766B2 publication Critical patent/JPH0145766B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 この発明は印加直流電源電圧の大きさによつて
利得の変化する電圧利得制御増幅装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage gain control amplifier whose gain changes depending on the magnitude of an applied DC power supply voltage.

第1図は従来の電圧利得制御増幅装置の一例を
示す回路構成図で、1,2は差動対をなすnpnト
ランジスタ、3および4はそれぞれトランジスタ
1および2のベースに接続された第1および第2
の信号入力端子であり、トランジスタ1,2のエ
ミツタは直列接続された抵抗5および6を介して
互いに接続され、抵抗5と抵抗6との接続点と接
地点との間に電流源7が接続されている。8と9
とは差動対をなすnpnトランジスタで、両者のエ
ミツタは共通にトランジスタ1のコレクタに接続
されている。10と11とは差動対をなすnpnト
ランジスタで両者のエミツタは共通にトランジス
タ2のコレクタに接続されている。トランジスタ
8,9,10のコレクタはいずれも電源端子12
に接続され、トランジスタ11のコレクタは抵抗
13を介して電源端子12に接続されている。ト
ランジスタ8,11のベースは共通に第1の制御
電圧端子14に接続され、トランジスタ9,10
のベースは共通に第2の制御電圧端子15に接続
されている。そして、トランジスタ11のコレク
タからは出力端子16が引出されている。
FIG. 1 is a circuit configuration diagram showing an example of a conventional voltage gain control amplifier, in which 1 and 2 are NPN transistors forming a differential pair, and 3 and 4 are first and second transistors connected to the bases of transistors 1 and 2, respectively. Second
The emitters of transistors 1 and 2 are connected to each other via series-connected resistors 5 and 6, and a current source 7 is connected between the connection point of resistors 5 and 6 and the ground point. has been done. 8 and 9
are npn transistors forming a differential pair, and their emitters are commonly connected to the collector of transistor 1. 10 and 11 are NPN transistors forming a differential pair, and their emitters are commonly connected to the collector of transistor 2. The collectors of transistors 8, 9, and 10 are all connected to the power supply terminal 12.
The collector of the transistor 11 is connected to the power supply terminal 12 via a resistor 13. The bases of transistors 8 and 11 are commonly connected to the first control voltage terminal 14, and the bases of transistors 9 and 10 are connected in common to the first control voltage terminal 14.
The bases of the two are commonly connected to the second control voltage terminal 15. An output terminal 16 is drawn out from the collector of the transistor 11.

次に、この従来例の動作について説明する。ト
ランジスタ1および2並びに抵抗5および6並び
に電流源7で構成される差動増幅部の相互コンダ
クタンスをgn1とし、第1の制御電圧端子14に
印加される直流(DC)電圧をV1、第2の制御端
子15に印加されるDC電圧をV2、抵抗13の抵
抗値をRLとすれば、第1図に示す電圧利得制御
増幅装置の利得はV1−V2の値によつて第2図の
実線で示すような変化を示す。一方、電流源7の
電流値をIOとし電源端子12に印加されるDC電
源電圧をVCCとすれば出力端子16での出力DC
電位はV1−V2の値によつて第2図の破線で示す
ような変化を示す。
Next, the operation of this conventional example will be explained. Let g n1 be the mutual conductance of the differential amplification section composed of transistors 1 and 2, resistors 5 and 6, and current source 7, and let V 1 be the direct current (DC) voltage applied to the first control voltage terminal 14, and let V 1 be the direct current (DC) voltage applied to the first control voltage terminal . If the DC voltage applied to the control terminal 15 of FIG. 2 is V 2 and the resistance value of the resistor 13 is R L , then the gain of the voltage gain control amplifier shown in FIG. 1 depends on the value of V 1 - V 2 . The change is shown by the solid line in FIG. On the other hand, if the current value of the current source 7 is I O and the DC power supply voltage applied to the power supply terminal 12 is V CC , then the output DC at the output terminal 16 is
The potential changes as shown by the broken line in FIG. 2 depending on the value of V 1 -V 2 .

従来の電圧利得制御増幅装置は以上のように構
成されているので、V1−V2の値で利得を変化さ
せた場合、同時に出力のDC電位も変化するので、
次の増幅段への接続が困難であつたり、V1−V2
の変化分が、出力信号に重畳され、悪影響を及ぼ
すなどの欠点があつた。
The conventional voltage gain control amplifier is configured as described above, so when the gain is changed by the value of V 1 - V 2 , the DC potential of the output also changes at the same time.
Connection to the next amplification stage may be difficult, or V 1 −V 2
This has the disadvantage that the change in the output signal is superimposed on the output signal and has an adverse effect.

この発明は、上記のような従来のものの欠点を
除去するためになされたもので、制御電圧V1
V2により利得を変化させた場合に、出力DC電位
が変化しないような電圧利得制御増幅装置を提供
することを目的としている。
This invention was made to eliminate the drawbacks of the conventional ones as described above, and the control voltage V 1
It is an object of the present invention to provide a voltage gain control amplifier in which the output DC potential does not change when the gain is changed by V2 .

第3図はこの発明の一実施例を示す回路構成図
で、第1図の従来例と同等部分は同一符号で示し
その説明を省略する。この実施例ではトランジス
タ11のコレクタ回路には電源端子12と抵抗1
3との間にトランジスタ17が挿入され、そのコ
レクタは電源端子12に、エミツタは抵抗13に
接続されている。トランジスタ9,10のコレク
タは共通に接続されているが直接電源端子12へ
は接続されず、抵抗18を介して電源端子12に
接続されており、かつこの共通接続コレクタはト
ランジスタ17のベースに接続されている。
FIG. 3 is a circuit configuration diagram showing an embodiment of the present invention, in which parts equivalent to those of the conventional example shown in FIG. In this embodiment, the collector circuit of the transistor 11 includes a power supply terminal 12 and a resistor 1.
A transistor 17 is inserted between the transistor 3 and the transistor 17, the collector of which is connected to the power supply terminal 12, and the emitter of which is connected to the resistor 13. The collectors of the transistors 9 and 10 are commonly connected, but not directly connected to the power supply terminal 12, but are connected to the power supply terminal 12 via a resistor 18, and this commonly connected collector is connected to the base of the transistor 17. has been done.

以上のように構成されたこの実施例になる電圧
利得制御増幅装置では、V1−V2の値に対する利
得の変化は第4図の実線に示すように従来例と全
く同等である。次に、V1−V2の値に対する出力
DC電位の変化について述べる。第1の信号入力
端子3および第2の信号入力端子4の直流バイア
ス電圧が等しいとすれば、トランジスタ1のコレ
クタ電流とトランジスタ2のコレクタ電流とは等
しく、それぞれIO/2となる。トランジスタ8の
コレクタ電流(IC8)とトランジスタ9のコレク
タ電流(IC9)はV1−V2の値によつて変化するが
IC8=α・IO/2とすればIC9=(1−α)・IO/2
(ただし0≦α≦1)となる。同様にトランジス
タ10のコレクタ電流(IC10)とトランジスタ1
1のコレクタ電流(IC11)とはIC10=(1−α)・
IO/2、IC11=α・IO/2となる。抵抗18の抵
抗値をR1とすれば、トランジスタ17のベース
電位VBはVB=VCC−R1(IC9C10)=VCC−R1(1−
α)IOとなるので、出力端子16での出力DC電
位VOは VO=VB−VBE−RLIC11=VCC−R1(1−α)IO−VBE−RL
αIO/2=VCC−VBE −{R1(1−α)+RLα/2}IO=VCC−VBE−〔R1
{(RL/2)−R1}α〕IO となる。ただしVBEはトランジスタ17のベー
ス・エミツタ間電圧である。従つて、RL/2=
R1とすればVO=VCC−VBE−R1IOとなり、αに無
関係、すなわち、制御電圧によつて出力DC電位
VOは変化しなくなる。この様子を第4図に破線
で示す。
In the voltage gain control amplifier of this embodiment configured as described above, the change in gain with respect to the value of V 1 -V 2 is completely the same as in the conventional example, as shown by the solid line in FIG. Then the output for the value of V 1 − V 2
We will discuss changes in DC potential. If the DC bias voltages of the first signal input terminal 3 and the second signal input terminal 4 are equal, the collector current of the transistor 1 and the collector current of the transistor 2 are equal, and each becomes I O /2. The collector current of transistor 8 (I C8 ) and the collector current of transistor 9 (I C9 ) change depending on the value of V 1 - V 2 .
If I C8 = α・I O /2, then I C9 = (1-α)・I O /2
(However, 0≦α≦1). Similarly, the collector current of transistor 10 (I C10 ) and transistor 1
The collector current (I C11 ) of 1 is I C10 = (1-α)・
I O /2, I C11 = α・I O /2. If the resistance value of the resistor 18 is R 1 , the base potential V B of the transistor 17 is V B = V CC −R 1 (I C9 + C10 ) = V CC −R 1 (1−
α) I O , so the output DC potential V O at the output terminal 16 is V O = V B − V BE −R L I C11 = V CC −R 1 (1−α) I O − V BE −R L
αI O /2=V CC −V BE −{R 1 (1−α)+R L α/2}I O =V CC −V BE −[R 1 +
{(R L /2)−R 1 }α]I O. However, V BE is the base-emitter voltage of the transistor 17. Therefore, R L /2=
If R 1 , then V O = V CC −V BE −R 1 I O , which is independent of α, that is, the output DC potential depends on the control voltage.
V O will no longer change. This state is shown by the broken line in FIG.

なお、入力端子3,4間に交流信号電圧が印加
された場合、トランジスタ9のコレクタ電流IC9
の変化量はトランジスタ10のコレクタ電流IC10
の変化量とは位相が180゜異なり、大きさが等しい
ので合計電流は変化せずトランジスタ17のベー
ス電位VBの変化としては現われないので、出力
DC電位VOにも現われることはない。
Note that when an AC signal voltage is applied between input terminals 3 and 4, the collector current of transistor 9 I C9
The amount of change in is the collector current I C10 of transistor 10
Since the phase is 180° different from the amount of change in and the magnitude is the same, the total current does not change and does not appear as a change in the base potential V B of transistor 17, so the output
It also does not appear at the DC potential VO .

なお、上記実施例ではnpnトランジスタで構成
される電圧利得制御増幅装置について示したが、
npnトランジスタによつて構成してもよい。
In addition, although the above embodiment shows a voltage gain control amplifier device composed of npn transistors,
It may also be configured with an npn transistor.

また、上記実施例では制御電圧をDC電圧に限
つて説明したが、交流電圧でもよく、さらにま
た、この増幅器の出力信号を整流した信号で制御
すれば、自動利得制御(AGC)増幅器ともなる。
Further, in the above embodiment, the control voltage is limited to a DC voltage, but an AC voltage may be used. Furthermore, if the output signal of this amplifier is controlled by a rectified signal, it can also be an automatic gain control (AGC) amplifier.

以上のように、この発明によれば、制御電圧に
よる出力DC電位の変動をなくす回路を付加した
ので、次段への接続が容易になる効果がある。
As described above, according to the present invention, since a circuit is added to eliminate fluctuations in the output DC potential due to the control voltage, there is an effect that connection to the next stage is facilitated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電圧利得制御増幅装置の一例を
示す回路構成図、第2図はこの従来例の利得制御
電圧と利得および出力DC電位との関係を示す特
性図、第3図はこの発明の一実施例を示す回路構
成図、第4図はこの実施例の利得制御電圧と利得
および出力DC電位との関係を示す特性図である。 図において、1は第1のトランジスタ、2は第
2のトランジスタ、3,4は信号入力端子、8は
第3のトランジスタ、9は第4のトランジスタ、
10は第5のトランジスタ、11は第6のトラン
ジスタ、13はコレクタ抵抗、14,15は利得
制御電圧端子、17は第7のトランジスタ、18
は共通コレクタ抵抗である。なお、図中同一符号
は同一または相当部分を示す。
Fig. 1 is a circuit configuration diagram showing an example of a conventional voltage gain control amplifier, Fig. 2 is a characteristic diagram showing the relationship between the gain control voltage, gain, and output DC potential of this conventional example, and Fig. 3 is a diagram of the present invention. FIG. 4 is a circuit configuration diagram showing one embodiment of the present invention, and FIG. 4 is a characteristic diagram showing the relationship between the gain control voltage, gain, and output DC potential of this embodiment. In the figure, 1 is a first transistor, 2 is a second transistor, 3 and 4 are signal input terminals, 8 is a third transistor, 9 is a fourth transistor,
10 is a fifth transistor, 11 is a sixth transistor, 13 is a collector resistor, 14 and 15 are gain control voltage terminals, 17 is a seventh transistor, 18
is the common collector resistance. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 信号入力に対して差動増幅動作をする第1お
よび第2のトランジスタ、利得制御電圧によつて
電流配分比が変えられるエミツタ結合の第1の差
動回路を構成するとともに該エミツタ結合部が上
記第1のトランジスタのコレクタに接続され上記
第1のトランジスタのコレクタ電流を供給する第
3および第4のトランジスタ、上記利得制御電圧
によつて電流配分比が変えられるエミツタ結合の
第2の差動回路を構成するとともに該エミツタ結
合部が上記第2のトランジスタのコレクタに接続
され上記第2のトランジスタのコレクタ電流を供
給する第5および第6のトランジスタ、上記利得
制御電圧によつて同相に動作する上記第4および
第5のトランジスタのコレクタに共通に接続され
た共通コレクタ抵抗、並びに上記第4および第5
のトランジスタの上記共通に接続されたコレクタ
にベースが接続されエミツタがコレクタ抵抗を介
して上記第6のトランジスタのコレクタに接続さ
れて上記第6のトランジスタのコレクタ回路を構
成する第7のトランジスタを備えたことを特徴と
する電圧利得制御増幅装置。
1. A first and second transistor that performs a differential amplification operation with respect to a signal input constitutes an emitter-coupled first differential circuit whose current distribution ratio is changed by a gain control voltage, and the emitter-coupled portion third and fourth transistors connected to the collector of the first transistor and supplying the collector current of the first transistor; an emitter-coupled second differential transistor whose current distribution ratio is changed by the gain control voltage; fifth and sixth transistors constituting a circuit and whose emitter coupling portions are connected to the collector of the second transistor and supplying the collector current of the second transistor, operating in phase by the gain control voltage; a common collector resistor commonly connected to the collectors of the fourth and fifth transistors;
a seventh transistor whose base is connected to the commonly connected collectors of the transistors and whose emitter is connected to the collector of the sixth transistor via a collector resistor to constitute a collector circuit of the sixth transistor. A voltage gain control amplifier characterized by:
JP6437282A 1982-04-15 1982-04-15 Voltage gain control amplification device Granted JPS58181310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6437282A JPS58181310A (en) 1982-04-15 1982-04-15 Voltage gain control amplification device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6437282A JPS58181310A (en) 1982-04-15 1982-04-15 Voltage gain control amplification device

Publications (2)

Publication Number Publication Date
JPS58181310A JPS58181310A (en) 1983-10-24
JPH0145766B2 true JPH0145766B2 (en) 1989-10-04

Family

ID=13256386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6437282A Granted JPS58181310A (en) 1982-04-15 1982-04-15 Voltage gain control amplification device

Country Status (1)

Country Link
JP (1) JPS58181310A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62117404A (en) * 1985-11-18 1987-05-28 Hitachi Denshi Ltd Variable gain amplifier circuit
JP3061674B2 (en) * 1992-01-23 2000-07-10 アルプス電気株式会社 Gain control circuit
US6987419B2 (en) * 2003-07-07 2006-01-17 M/A-Com, Inc. Absorptive microwave single pole single throw switch
US7547993B2 (en) 2003-07-16 2009-06-16 Autoliv Asp, Inc. Radiofrequency double pole single throw switch

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282303A (en) * 1975-12-29 1977-07-09 Matsushita Electric Ind Co Ltd Gain controller

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282303A (en) * 1975-12-29 1977-07-09 Matsushita Electric Ind Co Ltd Gain controller

Also Published As

Publication number Publication date
JPS58181310A (en) 1983-10-24

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