JP2861226B2 - Clock signal output circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an RTL (resistance transistor logic) circuit, and more particularly to a clock signal output circuit.

[Prior Art] FIG. 6 is a circuit diagram of a conventional example of such a clock signal output circuit.

First and second transistors connected to a common emitter
The current source _IS is connected to the common emitter of Q ₁ and Q ₂ , and the base of the first transistor Q ₁ is connected to the positive-phase clock signal input terminal CKIN
Is connected to the second base of the transistor Q ₂ is connected to the negative phase clock input signal terminal ▲ ▼, the first collector of the transistor Q ₁ is the base of the first resistor R ₁ and the fifth transistor Q ₅ is connected, the collector of the second transistor Q ₂ is connected to the base of the second resistor R ₂ and the fourth transistor Q _4, the first, second resistor R _1, the other end of R ₂ are both a reference potential And the emitters of the fourth and fifth transistors Q ₄ and Q ₅ are connected to the positive-phase clock output CKOUT and the negative-phase clock output ▲ ▼, respectively.
The collectors of Q ₄ and Q ₅ are both connected to the power supply V _CC .

Figure 4 Figure shows a sixth diagram showing an example of a shift register with a clock signal output circuit of Figure, Figure 5 is the first to example of the fourth flip-flop FF ₁ to ff ₄ in FIG. 4 It is.

Flip-flop FF ₁ to ff _4, the resistance and R _9, the transistor Q _8, Q ₉ whose emitter is connected, is connected to the clock terminal CK emitter via a resistor R _9, base each data input terminal D, And the collectors are connected to the bases of the transistors Q ₉ and Q ₈ , respectively.
Q and _10, Q _11, a power source V _CC and the transistor Q ₈ resistor R ₃ connected in series between the collector of, R _4, resistor connected between the collectors of the transistors Q ₁₀ of the transistor Q ₈ and R _5, a resistor R _6, R _7, which are connected in series between the collector of the power supply V _CC and the transistor Q _9, a resistor R ₈ connected between the collectors of the transistors Q ₁₁ of the transistor Q ₉ made, the connection point of the resistors R ₃ and R _4, the connection point of the resistors R ₆ and R ₇ has respective data output terminals, and Q.

[Problems to be Solved by the Invention] FIG. 7 is an operation waveform diagram of the shift register shown in FIG. The solid line and broken line in FIG. 7 (a) are the positive phase clock signal input and negative phase clock signal input of the clock signal output circuit, respectively, and the solid line and broken line in FIG. 7 (b) are the normal phase clock signal of the clock signal output circuit, respectively. The output, the negative phase clock signal output, the solid line and the broken line in FIG. 7 (c) are examples of signals applied to the data input IN and the inverted input ▲ ▼ of the shift register, respectively. The solid line and the broken line in FIG. FIG. 3 is a diagram showing a normal phase output waveform and a negative phase output waveform of a shift register.

As shown in FIG. 7D, in the conventional example, a large trigger noise is generated in the output. This is because, as shown in FIG. 7 (b), when the output of the normal phase clock signal and the output of the negative phase clock signal which are the outputs of the clock signal output circuit are inverted, both become active.

An object of the present invention is to provide a clock signal output circuit with less trigger noise.

[Means for Solving the Problems] A clock signal output circuit according to the present invention includes first, second, and third transistors connected to a common emitter.
The base of the second transistor is connected to the positive-phase clock signal input and the negative-phase clock signal input, respectively, and the base of the third transistor is connected to the DC bias source. Current supply means is connected to the common emitter of the transistors, and the output is taken out from the collectors of the first and second transistors.

[Operation] Since the current flows through the third transistor while the positive-phase clock input signal and the negative-phase clock input signal are inverted and the high and low levels are switched, the output of the positive-phase clock signal output is Neither is active when the inverted phase clock signal output is inverted.

Therefore, in the shift register using the clock signal output circuit of the present invention, the output trigger noise is small.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a clock signal output circuit according to a first embodiment of the present invention.

This embodiment is different from the prior art shown in FIG.
Transistor Q _1, comprises a third transistor Q ₃ which further is common emitter connected to the common emitter of Q _2, the collector of the third transistor Q ₃ are connected to the reference potential point, third
Base of the transistor Q ₃ are connected to the DC bias source V _B.

Here, the value of the DC bias source V _B is set to be lower than the midpoint of about 100~200mV high and low level and the high level from the low level of the clock signal applied to the input.

Next, the operation when the clock signal output circuit shown in FIG. 1 is used for the shift register shown in FIG. 4 will be described.

FIG. 2 is a diagram showing operation waveforms when the clock signal output circuit of this embodiment is used for the shift register of FIG. Second
The solid line and the broken line in FIG. 2A are the positive phase clock signal input and the negative phase input of the clock signal output circuit, respectively, and the solid line and broken line in FIG. 2B are the normal phase and negative phase clock signal output of the clock signal output circuit, respectively. , The solid line and the broken line in FIG. 2 (c) indicate the data input IN and the inverted data input of the shift register, respectively.
FIG. 3D is a diagram showing an example of a signal applied to ▼, and a solid line and a broken line in FIG.

(1) As shown in FIG. 2 (d), in the shift register using the clock signal output circuit of this embodiment, the trigger noise is reduced in the output. This is because, as shown in FIG. 2B, when the output of the normal phase clock signal and the output of the negative phase clock signal, which are the outputs of the clock signal output circuit, are inverted, neither of them becomes active. That is,
In the clock signal output circuit shown in FIG. 1, the third transistor Q ₃ is turned on while the positive-phase clock input signal and the negative-phase clock input signal are inverted and the high and low levels are switched.
This is because a current is flowing through.

FIG. 3 is a circuit diagram of a clock signal output circuit according to a second embodiment of the present invention.

The example shown in FIG. 3 is different from the example shown in FIG. 1 in that the connection of the first and second resistors R ₁ and R _{2 on} the reference potential point side is not directly connected to the reference potential point, but is diode-connected. The sixth and seventh transistors Q ₆ and Q ₇ are connected to a reference potential point via a series circuit.

This is to obtain a stable driving current over a wide temperature range when driving the flip-flop shown in FIG.

[Effects of the Invention] As described above, the present invention has an effect that the trigger noise of the RTL circuit can be reduced by including the third transistor and the DC bias source.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock signal output circuit according to a first embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the first embodiment, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a circuit diagram of a shift register, FIG. 5 is a circuit diagram of a flip-flop, FIG. 6 is a circuit diagram of a conventional example of a clock signal output circuit, and FIG. FIG. 6 is a diagram for explaining the operation of the conventional example of FIG. 6. Q _{1 to} Q ₁₁ … Transistors R ^{1 to} R ₉ … Resistance I _s … Current source V _B … DC bias source CKIN… Positive phase clock signal input terminal ▲ ▼… Negative phase clock signal input terminal CKOUT … Normal phase clock signal output terminal ▲ ▼… Negative phase clock signal output terminal FF _{1 to} FF ₄ …… Flip-flop IN, ▲ ▼… Input terminal OUT, ▲ ▼ …… Output terminal

Claims (1)

(57) [Claims] 1. A first, second, and third common emitter connected.
, The bases of the first and second transistors are respectively connected to the positive-phase clock signal input and the negative-phase clock signal input, and the base of the third transistor is connected to the DC bias source. Current supply means is connected to a common emitter of the second and third transistors,
A clock signal output circuit from which outputs are taken from the collectors of the first and second transistors.