JPS6354246B2 - - Google Patents
Info
- Publication number
- JPS6354246B2 JPS6354246B2 JP56110534A JP11053481A JPS6354246B2 JP S6354246 B2 JPS6354246 B2 JP S6354246B2 JP 56110534 A JP56110534 A JP 56110534A JP 11053481 A JP11053481 A JP 11053481A JP S6354246 B2 JPS6354246 B2 JP S6354246B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- input
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
- H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
本発明はセツト又はリセツト信号によつて、論
理状態を任意に制御し得る所謂セツト・リセツト
フリツプフロツプに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called set/reset flip-flop whose logic state can be arbitrarily controlled by a set or reset signal.
セツト・フリツプフロツプリセツト（以下
RSFと略記）は、順序型論理回路の最も基本的
な構成要素であるため従来よりいくつかの回路構
成が提案されている。 Set/Flip/Preset (below)
Since RSF (abbreviated as RSF) is the most basic component of sequential logic circuits, several circuit configurations have been proposed.
第１図は、電流切換型論理回路による最も一般
的なRSFを示す。同図の動作を簡単に説明する
と、例えばセツト入力Ｓと、リセツト入力Ｒが共
に低レベルの時、即ち、データ保持状態の時トラ
ンジスタQ3がオン、トランジスタQ2がオフして
いるとする。 FIG. 1 shows the most common RSF using current switched logic circuits. To briefly explain the operation in the figure, it is assumed that, for example, when both the set input S and the reset input R are at a low level, that is, when data is held, transistor Q3 is on and transistor Q2 is off.
従つて、定電流源CSの電流の大部分は、トラ
ンジスタQ3を流れ真値出力OUTが低レベル、相
補出力が高レベルになつている。 Therefore, most of the current of the constant current source CS flows through the transistor Q3 , so that the true value output OUT is at a low level and the complementary output is at a high level.
次に、セツト入力Ｓが高レベルに変化すると、
定電流源CSの電流の一部が、トランジスタQ1に
も分流する。このため、相補出力の電位が
降下し、逆に真値出力OUTの電位は、トランジ
スタQ3の電流が減少した事により、上昇する。 Next, when the set input S changes to high level,
A portion of the current from the constant current source CS is also shunted to the transistor Q1 . Therefore, the potential of the complementary output falls, and conversely, the potential of the true value output OUT rises due to the decrease in the current of the transistor Q3 .
一方、トランジスタQ3のベースが相補出力
OUTに接続されている事から、相補出力の
電位低下に伴つて、トランジスタQ3を流れる電
流はいよいよ減少し、遂には、トランジスタQ3
がオフし、一方トランジスタQ1がオンの状態に
なる。従つて、真値出力OUTは高レベル、相補
出力は低レベルの状態に変化する。 On the other hand, the base of transistor Q 3 is the complementary output
Since it is connected to OUT, the current flowing through transistor Q 3 gradually decreases as the potential of the complementary output decreases, and finally, transistor Q 3
is turned off, while transistor Q1 is turned on. Therefore, the true value output OUT changes to a high level and the complementary output changes to a low level.
この状態から、セツト入力Ｓのレベルが低レベ
ルに戻つても、トランジスタQ1の電流が、トラ
ンジスタQ2に切換わるだけで、各出力の状態は
変化しない。 Even if the level of the set input S returns to a low level from this state, the current of the transistor Q1 is simply switched to the transistor Q2 , and the state of each output does not change.
上記が、第１図のRSFを「セツト」する状況
である。 The above is the situation in which the RSF of FIG. 1 is "set."
一方、「リセツト」する状況は、リセツト入力
Ｒを高レベルに変化させると、上記と同様の変化
で、トランジスタQ2がオフ、トランジスタQ3が
オンの状態になる。 On the other hand, in a "reset" situation, when the reset input R is changed to a high level, the transistor Q2 is turned off and the transistor Q3 is turned on, with the same change as described above.
ここで、上記「セツト」又は「リセツト」する
場合の、セツト入力Ｓ、リセツト入力Ｒの閾値に
ついて考える。 Here, the threshold values of the set input S and the reset input R in the case of the above-mentioned "set" or "reset" will be considered.
上記例の初期状態、即ち、トランジスタQ3が
オン、トランジスタQ2がオフしていて、セツト
入力Ｓ、リセツト入力Ｒが共に低レベルの状態か
ら、「セツト」する場合を例として考える。この
場合トランジスタQ2と、トランジスタQ4は差し
当たり動作と関係がないので無視すると、第２図
の等価回路が書ける。 Let us consider as an example the case where "setting" is performed from the initial state of the above example, that is, transistor Q 3 is on, transistor Q 2 is off, and both set input S and reset input R are at low level. In this case, the equivalent circuit shown in FIG. 2 can be written by ignoring transistor Q 2 and transistor Q 4 because they have no relation to the operation for the time being.
第２図で、トランジスタQ3のベース電位は、
トランジスタQ1がオフして、負荷抵抗RL1の電圧
降下が、ほぼφである事から、上側電源値とほぼ
同一になつている。一方、トランジスタQ1のベ
ースにセツト入力Ｓを入力して、トランジスタ
Q1をオンさせるには、通常の電流切換型回路と
同様に、対トランジスタのベース電位を少なくと
も同一レベルまで引き上げなければならない。 In Figure 2, the base potential of transistor Q3 is
Since the transistor Q 1 is turned off and the voltage drop across the load resistor R L1 is approximately φ, it is approximately the same as the upper power supply value. On the other hand, by inputting the set input S to the base of transistor Q1 , the transistor
To turn on Q 1 , the base potentials of the paired transistors must be raised to at least the same level, as in normal current-switching circuits.
従つて、セツト入力Ｓの高レベルは、上側電源
値と同一か、それ以上にしなければ、トランジス
タQ3に流れる電流を、トランジスタQ1に切換え
られない。 Therefore, unless the high level of the set input S is equal to or higher than the upper power supply value, the current flowing through the transistor Q3 cannot be switched to the transistor Q1 .
ただし、トランジスタQ3のベース電位が外部
電圧源で与えられる通常の電流切換型回路と異な
り、トランジスタQ1のコレクタからの帰還電圧
として与えられているため、セツト入力Ｓの閾値
は、上側電源値より若干低くはなる。 However, unlike a normal current switching type circuit in which the base potential of transistor Q3 is given by an external voltage source, it is given as a feedback voltage from the collector of transistor Q1 , so the threshold of set input S is set to the upper power supply value. It will be slightly lower.
上記の様に、第１図に示されたRSFでは、セ
ツト及びリセツト入力の閾値電位が、通常の電流
切換型論理回路よりかなり高くなる。 As mentioned above, in the RSF shown in FIG. 1, the threshold potentials of the set and reset inputs are significantly higher than in conventional current switched logic circuits.
このことは、セツト及びリセツトの感度が低い
事であり、好ましくない。 This is undesirable since the sensitivity of setting and resetting is low.
上記の欠点を補うため、第３図に示す様に、コ
レクタ負荷抵抗RL3，RL4の共通接点と、上側電
圧源との間に、レベルシフト抵抗Rccを挿入し、
実効的に上側電源値の電圧値を下げた回路が案出
されている。 In order to compensate for the above drawbacks, a level shift resistor Rcc is inserted between the common contact of the collector load resistors R L3 and R L4 and the upper voltage source, as shown in Figure 3.
A circuit has been devised that effectively lowers the voltage value of the upper power supply value.
第３図の回路では、レベルシフト抵抗Rccに常
に定電流源CSの電流が流れることによる電圧降
下が生じているため、トランジスタQ5〜Q8から
見た、実効的な上側電圧源電圧値が低下する。従
つて、セツト及びリセツト入力の閾値は、RSF
の外から見た場合、レベルシフト抵抗Rccの電圧
降下分だけ下がり、セツト及びリセツトの感度が
向上する。 In the circuit shown in Figure 3, a voltage drop occurs due to the constant current source CS constantly flowing through the level shift resistor Rcc, so the effective upper voltage source voltage value as seen from transistors Q5 to Q8 is descend. Therefore, the set and reset input thresholds are RSF
When viewed from the outside, the voltage drops by the voltage drop across the level shift resistor Rcc, improving the sensitivity of set and reset.
しかし、第３図の回路では、真値出力OUT、
相補出力の高レベルが、レベルシフト抵抗
Rccの電圧降下分だけ必ず下がるため、RSFの出
力レベルが、通常の電流切換型回路と異なつてし
まう不都合がある。 However, in the circuit shown in Figure 3, the true value output OUT,
The high level of the complementary output is the level shift resistor.
Since the Rcc voltage drop is always reduced, the RSF output level is inconveniently different from that of a normal current switching type circuit.
特に論理振幅の小さい場合などは、RSFの高
レベル出力と、次段の電流切換型回路の閾値とが
近づき過ぎる事による動作不全を生ずる可能性が
ある。 Particularly when the logic amplitude is small, there is a possibility that malfunction may occur due to the high level output of the RSF being too close to the threshold of the current switching circuit in the next stage.
本発明の目的は、従来のRSFの、上記欠点を
なくし、入力閾値電圧を下げて、セツト及びリセ
ツト入力に対する感度を向上させると共に、出力
レベルの特異性をなくし入／出力条件を通常の電
流切換え型論理回路と同等にする事にある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks of the conventional RSF, lower the input threshold voltage, improve the sensitivity to set and reset inputs, eliminate the specificity of the output level, and change the input/output conditions to normal current switching. The purpose is to make it equivalent to a type logic circuit.
このため本発明は、エミツタを相互に接続した
一対のトランジスタの内、第１のトランジスタの
コレクタを、第１の抵抗を介して上側電源に、他
の一方の、第２のトランジスタのコレクタを、第
２の抵抗を介して上側電源に接続すると共に、該
エミツタ相互接続点に定電流源を接続した電流切
換え型論理回路において、該第１のトランジスタ
のコレクタに、コレクタを、該第２のトランジス
タのコレクタにベースを、各々接続した第３のト
ランジスタと、該第１のトランジスタのコレクタ
にベースを、該第２のトランジスタのコレクタに
コレクタを、各々接続した第４のトランジスタと
を設け、該第３、第４のトランジスタのエミツタ
を、それぞれ、第３、第４の抵抗を介して、前記
第１と第２のトランジスタのエミツタ相互接続点
に接続した事を特徴とする。 Therefore, in the present invention, of a pair of transistors whose emitters are connected to each other, the collector of the first transistor is connected to the upper power supply via the first resistor, and the collector of the other transistor, the second transistor, is connected to the upper power supply through the first resistor. In a current switching type logic circuit connected to an upper power supply via a second resistor and a constant current source connected to the emitter interconnection point, the collector is connected to the collector of the first transistor, and the collector is connected to the collector of the first transistor. a third transistor having its base connected to the collector of the first transistor, and a fourth transistor having its base connected to the collector of the first transistor, and the collector connected to the collector of the second transistor, respectively; 3. The emitter of the fourth transistor is connected to the emitter interconnection point of the first and second transistors via third and fourth resistors, respectively.
本発明の実施例を、第４図に示す。 An embodiment of the invention is shown in FIG.
第４図の様に、トランジスタQ10，Q11のエミ
ツタに、エミツタ抵抗RE1，RE2を付加した事に
より、トランジスタQ10，Q11のエミツタ電位は
トランジスタQ9，Q12のエミツタ電位より若干高
くなる。 As shown in Figure 4, by adding emitter resistors R E1 and R E2 to the emitters of transistors Q 10 and Q 11 , the emitter potential of transistors Q 10 and Q 11 is lower than the emitter potential of transistors Q 9 and Q 12 . Slightly more expensive.
上記により、例えば、第４図で相補出力
が高レベルで、トランジスタQ11がオンしている
場合、トランジスタQ11のベース電位が等価的に
エミツタ抵抗RE2の電圧降下分だけ下がつて見え
るため、セツト入力Ｓに高レベルを印加して、ト
ランジスタQ9に定電流源CSの電流が分流し、相
補出力の電位が下がつた時、容易に、トラ
ンジスタQ11がオフする。 As a result of the above, for example, in Figure 4, when the complementary output is at a high level and transistor Q 11 is on, the base potential of transistor Q 11 appears to drop equivalently by the voltage drop of emitter resistor R E2 . When a high level is applied to the set input S, the current from the constant current source CS is shunted to the transistor Q9 , and the potential of the complementary output drops, the transistor Q11 is easily turned off.
この様子を入／出力特性と入力／閾値特性とで
示したものが第５図である。 FIG. 5 shows this situation in terms of input/output characteristics and input/threshold characteristics.
同図で、曲線Ａ−Ｂ−Ｃ−Ｄの実線で示したも
のが、エミツタ抵抗RE1，RE2を０、即ち、第１
図の従来回路における特性で、セツト入力Ｓの入
力電圧Vinが低レベル（同図左側）から上昇する
と出力OUTの電圧は点Ａ→Ｂ→Ｃを通つて、原
点０に至る。 In the figure, the solid line A-B-C-D indicates that the emitter resistances R E1 and R E2 are 0, that is, the first
In the characteristic of the conventional circuit shown in the figure, when the input voltage Vin of the set input S rises from a low level (on the left side of the figure), the voltage of the output OUT passes through points A→B→C and reaches the origin 0.
従つて、入力閾値ａは点Ｄ→Ｂに変化する。 Therefore, the input threshold value a changes from point D to point B.
一方、通常の電流切換え型回路の入力閾値は、
入／出力振幅の中点、第５図のC′点付近にあるか
ら、第１図の入力閾値Ｂ点がかなり高い所にある
事がわかる。 On the other hand, the input threshold of a normal current switching type circuit is
Since it is near the midpoint of the input/output amplitude, point C' in FIG. 5, it can be seen that the input threshold point B in FIG. 1 is quite high.
次に、第４図の、本発明による回路のセツト入
力Ｓの入力電圧Vinに対する出力OUTの特性は、
第５図の点A′−B′−C′−D′で示した特性となり、
入力閾値ｂは点D′からB′に変化する。 Next, the characteristics of the output OUT with respect to the input voltage Vin of the set input S of the circuit according to the present invention in FIG. 4 are as follows:
The characteristics are shown by points A'-B'-C'-D' in Figure 5,
The input threshold b changes from point D' to B'.
従つて、本発明による回路の入力閾値B′点は
適当なエミツタ抵抗値により、通常の電流切換型
回路の閾値と同等になる事がわかる。 Therefore, it can be seen that the input threshold point B' of the circuit according to the present invention can be made equivalent to the threshold value of a normal current switching type circuit by using an appropriate emitter resistance value.
なお、入力レベルが、高レベルから低レベルに
変化する時の閾値は、第５図のＤ及びD′点であ
るが、同図の様に、エミツタ抵抗RE1，RE2の付
加の効果は少なく、従来回路（Ｄ点）でも、本発
明の回路（D′点）でも大差ない。即ち、セツト
及びリセツト入力の、低レベルの上限値には変化
がない。 The threshold values when the input level changes from high level to low level are points D and D' in Figure 5, but as shown in the figure, the effect of adding emitter resistors R E1 and R E2 is There is little difference between the conventional circuit (point D) and the circuit of the present invention (point D'). That is, there is no change in the low level upper limit of the set and reset inputs.
一方、出力レベルについては、第４図に示す様
に、コレクタ側の回路が、通常の電流切換型論理
回路と全く同一である事から、通常の電流切換型
回路と同等のレベルになる事は明らかである。 On the other hand, regarding the output level, as shown in Figure 4, the collector side circuit is exactly the same as a normal current switching type logic circuit, so it is unlikely that the output level will be the same as that of a normal current switching type circuit. it is obvious.
以上の様に、本発明によるRSFは、適当なエ
ミツタ抵抗を付加する事により、入力閾値、出力
レベル共、通常の電流切換型論理回路と同一の特
性を持ち、入力感度の高い安定な動作を期待でき
る。 As described above, by adding an appropriate emitter resistance, the RSF according to the present invention has the same characteristics as a normal current switching type logic circuit in terms of input threshold and output level, and can achieve stable operation with high input sensitivity. You can expect it.
なお、第４図に示した、本発明の実施例では
NPN型トランジスタを用いたが、PNP型トラン
ジスタによつても同様の効果が得られることは言
うまでもない。 In addition, in the embodiment of the present invention shown in FIG.
Although NPN type transistors were used, it goes without saying that similar effects can be obtained using PNP type transistors.
第１図は従来の、電流切換型RSF回路図、第
２図はセツト入力有効の状態の、第１図の等価回
路図、第３図は入力感度向上を図つた、概知の
RSF回路図、第４図は本発明によるRSFの実施
例を示す回路図、第５図は第１図及び第４図の
RSFの、入／出力特性および入力／閾値特性を
示す図である。
Q1〜Q12：トランジスタ（第１〜４図）、RL1〜
RL6：コレクタ負荷抵抗（第１〜４図）、CS：定
電流源（第１〜４図）、RE1，RE2：エミツタ抵抗
（第４図）、Ｓ：セツト入力端子（第１〜４図）、
Ｒ：リセツト入力端子（第１〜４図）、OUT：真
値出力端子（第１〜４図）、：相補出力端子
（第１〜４図）、Vin：入力電圧（第５図）、
Vout：出力電圧（第５図）。
Figure 1 is a conventional current-switching RSF circuit diagram, Figure 2 is an equivalent circuit diagram of Figure 1 with set input enabled, and Figure 3 is a conventional current-switching RSF circuit diagram.
RSF circuit diagram, FIG. 4 is a circuit diagram showing an embodiment of RSF according to the present invention, and FIG.
FIG. 3 is a diagram showing input/output characteristics and input/threshold characteristics of RSF. Q 1 ~ Q 12 : Transistor (Figures 1 to 4), R L1 ~
R L6 : Collector load resistance (Fig. 1 to 4), CS: Constant current source (Fig. 1 to 4), R E1 , R E2 : Emitter resistance (Fig. 4), S: Set input terminal (Fig. 1 to Figure 4),
R: Reset input terminal (Fig. 1 to 4), OUT: True value output terminal (Fig. 1 to 4), : Complementary output terminal (Fig. 1 to 4), Vin: Input voltage (Fig. 5),
Vout: Output voltage (Figure 5).
Claims (1)
タの内一方の第１のトランジスタのコレクタを、
第１の抵抗を介して電源に、他方の第２のトラン
ジスタのコレクタを第２の抵抗を介して電源に接
続すると共に、該エミツタ相互接続点に定電流源
を接続し、該第１のトランジスタのコレクタに、
コレクタを、該第２のトランジスタのコレクタに
ベースを各々接続した第３のトランジスタと、該
第１のトランジスタのコレクタにベースを、該第
２のトランジスタのコレクタに、コレクタを各々
接続した第４のトランジスタとを設け、該第３、
第４のトランジスタのエミツタをそれぞれ第３お
よび第４の抵抗を介して前記第１と第２のトラン
ジスタのエミツタ相互接続点に接続したことを特
徴とするフリツプフロツプ。1. Connect the collector of one of the first transistors of a pair of transistors whose emitters are connected to each other,
The collector of the other second transistor is connected to the power supply via the first resistor, and the collector of the other second transistor is connected to the power supply via the second resistor, and a constant current source is connected to the emitter interconnection point, and the collector of the other second transistor is connected to the power supply via the second resistor. to the collector of
a third transistor whose collector is connected to the collector of the second transistor, and a fourth transistor whose base is connected to the collector of the first transistor, and whose collector is connected to the collector of the second transistor, respectively; a transistor;
A flip-flop characterized in that the emitter of a fourth transistor is connected to the emitter interconnection point of the first and second transistors through third and fourth resistors, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56110534A JPS5812420A (en) | 1981-07-15 | 1981-07-15 | Flip-flop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56110534A JPS5812420A (en) | 1981-07-15 | 1981-07-15 | Flip-flop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5812420A JPS5812420A (en) | 1983-01-24 |
| JPS6354246B2 true JPS6354246B2 (en) | 1988-10-27 |
Family
ID=14538241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56110534A Granted JPS5812420A (en) | 1981-07-15 | 1981-07-15 | Flip-flop |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5812420A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209226A (en) * | 1982-05-31 | 1983-12-06 | Fujitsu Ltd | Set circuit |
-
1981
- 1981-07-15 JP JP56110534A patent/JPS5812420A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5812420A (en) | 1983-01-24 |
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