JPS6113413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an exclusive OR circuit using complementary transistors.

FIG. 1 shows a conventional example of an exclusive OR circuit using complementary transistors. In FIG. 1, the emitters of NPN transistors 1 and 2 are commonly connected to a resistor 3, and the logical sum (A+B) of input terminals 5 and 6 is obtained at a connection point 4. PNP transistor 7,
8 is commonly connected to the resistor 9 of the emitter, and the connection point 10 is the logical product (A and B) of the input terminals 5 and 6.
is obtained. The input at connection point 10 is NPN
A transistor 11 and resistors 12 and 13 perform level shifting and amplitude limitation, and output the signal to a connection point 14. Further, when the input at the connection point 14 is inverted and level shifted by the NPN transistor 15 and resistors 16 and 17, the negation (.) of the input from the connection point 10 is obtained at the connection point 18. PNP transistors 19 and 20 share the emitter with resistor 21
, and its connection point 22 has connection points 4 and 10.
logical product ((A+B)・=・B+A・)
is obtained, and this result is the exclusive OR (AB) of input terminals 5 and 6. In this way, the conventional exclusive OR circuit using complementary transistors has 8
Since the circuit requires two transistors and seven resistors, it has the disadvantage that it occupies a large area on a chip when integrated into a circuit. In addition, in the worst case, the operating time of the exclusive OR configured in this way is
The signal propagation time is the sum of the signal propagation time of the NOT circuit and the OR circuit, which has the drawback of requiring a large calculation time.

Furthermore, as a conventional example of an exclusive OR circuit, as shown in Japanese Patent Publication No. 15167/1983, two NPN transistors and two PNP transistors are used, and the number of parts is reduced compared to that in Fig. 1. Exclusive OR circuits with a small number of are also known. However, since this conventional example has wiring that intersects, it is not suitable for printing patterns on printed circuit boards or integrated circuits on silicon chips, and there are limits to miniaturization and integration of circuits. There is.

The present invention is characterized by using complementary transistors to construct an exclusive OR circuit with a small number of elements and no cross wiring, and its purpose is to increase the speed of calculation and increase the degree of integration. This will be explained in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which a first input terminal 25 is connected to a first NPN transistor 27 and a first
The second input terminal 26 is connected to the base of the second NPN transistor 29.
8 and the base of the second PNP transistor 30. The emitters of these four transistors are commonly connected, and 31 indicates the common connection point. The first and second NPN transistors 27 and 28 have collectors in common and are connected to a power supply terminal 34 of the first voltage source labeled +V.
It is connected to the. Furthermore, the first and second PNP
Transistors 29 and 30 have collectors in common and are connected to output terminal 33, and resistor 32.
to the ground terminal 35 of a second voltage source labeled GND.

The operation of the exclusive OR circuit configured as described above will be explained below. When the input terminals 25 and 26 both have a logic value of "0" (low level), the transistors 27 and 28 are cut off, and the transistors 29 and 3
0 is a conductive state. As a result, no current is supplied from the power supply terminal 34 to the resistor 32, and the output terminal 33 becomes "0".

Input terminal 25 is “1” (high level), input terminal 2
When 6 is "0", the transistors 27 and 30 become conductive, current is supplied from the power supply terminal 34 to the resistor 32, and the output terminal 33 becomes "1".

Input terminal 25 is “0”, input terminal 26 is “1”
In this case, the transistors 28 and 29 become conductive, current is supplied from the power supply terminal 34 to the resistor 32, and the output terminal 33 becomes "1".

When the input terminals 25 and 26 are both "1", the transistors 27 and 28 are turned on, and the transistors 29 and 30 are turned off. As a result, no current is supplied from the power supply terminal 34 to the resistor 32, and the output terminal 33 becomes "0".

As described above, exclusive OR is obtained by the circuit shown in FIG.

Note that in FIG. 2, transistors 27 and 28 are PNP transistors, and transistor 29 is
Similar functions can be obtained by using NPN transistors 30 and 30 as NPN transistors.

Further, FIG. 3 shows a second embodiment of the present invention.
This circuit differs from the embodiment shown in FIG. 2 in that the connection of the resistors is changed, so that exclusive OR negation can be obtained.

The operation will be explained below. Input terminal 36, 3
7 are both "0", the transistor 40,
41 is in a conductive state, and transistors 38 and 39 are in a cut-off state. As a result, since no current is supplied to the resistor 44 from the power supply terminal 45, "1" is obtained at the output terminal 42.

Input terminal 36 is “0”, input terminal 37 is “1”
In this case, transistors 39 and 40 are turned on, and transistors 38 and 41 are turned off.
As a result, a current is supplied from the power supply terminal 45 to the resistor 44 through the transistors 33 and 34, and "0" is obtained at the output terminal 42.

Input terminal 36 is “1”, input terminal 37 is “0”
In this case, transistors 38 and 41 are turned on, and transistors 39 and 40 are turned off.
As a result, the resistor 44 is connected to the resistor 4 from the power supply terminal 45.
A current is supplied to the transistor 4 through the transistors 38 and 41, and "0" is obtained at the output terminal 42.

When the input terminals 36 and 37 are both "1", the transistors 38 and 39 are in a conductive state, and the transistors 40 and 41 are in a cut-off state. As a result, since no current is supplied to the resistor 44 from the power supply terminal 45, "1" is obtained at the output terminal 42.

As described above, the negative () output of the exclusive OR is obtained by the circuit shown in FIG.

Note that in FIG. 3, transistors 38 and 39 are PNP transistors, and transistor 40 is
A similar function can be obtained by replacing 41 with an NPN transistor.

As explained above, the operation time of the exclusive OR circuit of the present invention is determined by the switching speed of only two cascaded transistors. Therefore, the exclusive OR circuit of the present invention can be faster than the conventional exclusive OR circuit. Further, the circuit of the present invention has the advantage of being suitable for high integration because the number of constituent elements is small, 4 transistors and 1 resistor, and the wiring does not cross each other.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. Figure 2: 25 and 26...input terminals, 27 and 28...NPN transistors, 29 and 3
0...PNP transistor, 32...Resistor, 33...
...Output terminal, 34...Power terminal, 35...Earth terminal, Figure 3: 36 and 37...Input terminal, 3
8 and 39...NPN transistor, 40 and 41...PNP transistor, 42...output terminal, 44...resistor, 45...power supply terminal, 46...
Earth terminal.

Claims (1)

[Claims] 1 The first and second NPN transistors and the first
All emitters (or all collectors) of the second PNP transistor are connected in common, and the bases of the first NPN transistor and the first PNP transistor are connected to the first input terminal, and the second NPN transistor and the first PNP transistor are connected to the first input terminal. A common base with the second PNP transistor is connected to the second input terminal, and a common connection point between the collectors (or emitters) of the first and second NPN transistors and the base of the first and second PNP transistors is connected to the second input terminal. A common connection in which said resistor and said resistor are connected by connecting one of the common connection points of the collector (or emitter) to a first voltage source through a resistor and the other directly to a second voltage source. An exclusive OR circuit characterized in that an exclusive OR circuit obtains an exclusive OR output of inputs applied to first and second input terminals between points.