JPS5833729B2 - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS5833729B2 JPS5833729B2 JP6806178A JP6806178A JPS5833729B2 JP S5833729 B2 JPS5833729 B2 JP S5833729B2 JP 6806178 A JP6806178 A JP 6806178A JP 6806178 A JP6806178 A JP 6806178A JP S5833729 B2 JPS5833729 B2 JP S5833729B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- signal output
- signal input
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、論理回路、特に信号入力線を複数組に区分す
ると共に1個以上のエミッタを有するトランジスタを用
い、回路構成素子数の少ない構成で所定の処理を行ない
得るようにした論理回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention divides a logic circuit, particularly a signal input line into a plurality of groups, and uses transistors each having one or more emitters, thereby making it possible to perform predetermined processing with a configuration with a small number of circuit components. The present invention relates to a logic circuit configured as follows.
従来のこの種の論理回路は、1組の信号入力線群と1組
の信号出力線群とで構成されていた。Conventional logic circuits of this type have been comprised of one set of signal input lines and one set of signal output lines.
第1図は、具体例として入力数7のダイオード論理回路
を示したもので、Ai(i=1〜7)は信号入力端子、
Liは信号入力線、Mj(j=1〜6)は信号出力線、
Dk(k=1〜12)はダイオード、Rjは抵抗、G1
はオア・ゲート、Xは信号出力端子である。FIG. 1 shows a diode logic circuit with seven inputs as a specific example, where Ai (i=1 to 7) is a signal input terminal;
Li is a signal input line, Mj (j = 1 to 6) is a signal output line,
Dk (k=1 to 12) is a diode, Rj is a resistor, G1
is an OR gate, and X is a signal output terminal.
該回路例では、Ai に加える入力変数をalvXでの
出力関数をXとすると、
である。In this circuit example, if the input variable to be added to Ai is alvX and the output function is X, then the following equation is obtained.
該回路における回路構成素子数は、ダイオード12個、
抵抗6個、オア・ゲート1個である。The number of circuit components in this circuit is 12 diodes,
There are 6 resistors and 1 OR gate.
このように従来の方法で回路を構成すると、入力数が多
い場合には回路構成素子数が非常に多くなり、また、各
々の信号出力線を共通結合することができないので集積
回路化した場合にはチップ上の占有面積が大きくなると
いう欠点があった。When configuring a circuit using the conventional method, the number of circuit components becomes extremely large when there are many inputs, and since it is not possible to connect each signal output line in common, it is difficult to configure the circuit in an integrated circuit. has the disadvantage that it occupies a large area on the chip.
本発明はこれらの欠点を除去するため、信号入力線群を
2組に分割し、信号出力線を共通結合できるようにした
もので、以下図面について詳細に説明する。In order to eliminate these drawbacks, the present invention divides the signal input line group into two groups so that the signal output lines can be commonly connected.The present invention will be described in detail with reference to the drawings below.
第2図はnpn形トランジスタを用いて構成した本発明
の実施例を示す。FIG. 2 shows an embodiment of the invention constructed using npn transistors.
第2図において、AI(1=1〜7)は信号入力端子、
Xは信号出力端子、N11.N12.N13゜N、4は
第1信号入力線群、N2□、 N22 、 N23は第
2信号入力線群、N31は信号出力線、G10.G12
゜G13.G14はインバータ、Trm (m−1〜4
)はトランジスタ、R7は抵抗である。In FIG. 2, AI (1=1 to 7) is a signal input terminal;
X is a signal output terminal, N11. N12. N13°N,4 is the first signal input line group, N2□, N22, N23 is the second signal input line group, N31 is the signal output line, G10. G12
゜G13. G14 is an inverter, Trm (m-1~4
) is a transistor, and R7 is a resistor.
第2図の回路の動作原理について説明する。The operating principle of the circuit shown in FIG. 2 will be explained.
信号入力端子A1における入力信号の状態をal、信号
出力端子Xにおける出力信号の状態をXとし、正論理で
考える。Let the state of the input signal at the signal input terminal A1 be al, and the state of the output signal at the signal output terminal X be X, and consider positive logic.
Xの値がHすなわち、信号出力fmNs 1上の信号の
状態がLとなるのはトランジスタTrmO内少くも1個
のトランジスタがオン状態にあるときである。The value of X becomes H, that is, the state of the signal on the signal output fmNs1 becomes L when at least one transistor in the transistor TrmO is in the on state.
たとえばトランジスタTr1がオン状態にあるための条
件はalがHで、かつが成りたつ。For example, the conditions for the transistor Tr1 to be on are that al is H and and.
つまり、第2図の回路の論理機能は第1図の回路と同等
である。That is, the logic function of the circuit of FIG. 2 is equivalent to that of the circuit of FIG.
それにも拘らず、回路構成素子数は第2図の回路の方が
少ない。Nevertheless, the number of circuit components is smaller in the circuit of FIG.
これは、第2図の各トランジスタTrm 1個あたり
の機能が第1図の対応する各信号出力線上に分布したダ
イオードの機能の総和と同等であり、かつ第2図では各
トランジスタのコレクタを1本の信号出力線N3、に共
通結合できるために第1図のオア・ゲートに相当する回
路素子が不要であるためである。This means that the function of each transistor Trm in Figure 2 is equivalent to the sum of the functions of diodes distributed on the corresponding signal output lines in Figure 1, and in Figure 2, the collector of each transistor is This is because a circuit element corresponding to the OR gate in FIG. 1 is not required because the circuit can be commonly coupled to the main signal output line N3.
上記の例で示したように、信号入力線を2群に分割し、
一方の入力線群を、1個以上のエミッタを有するトラン
ジスタ群のベースに1対1対応に結合し、他方の入力線
群を、該トランジスタのエミッタに結合し、信号出力を
該トランジスタのコレクタの共通結合により取り出すこ
とによって、回路構成素子数を低減することができる。As shown in the example above, the signal input lines are divided into two groups,
One input line group is coupled in a one-to-one correspondence to the base of a transistor group having one or more emitters, the other input line group is coupled to the emitter of the transistor, and the signal output is connected to the collector of the transistor. By extracting through common coupling, the number of circuit elements can be reduced.
ここでは特にnpn形トランジスタを用いて回路構成す
る場合について説明したが、上記考え方はpnp形トラ
ンジスタで回路を構成する場合にも適用できる。Although the case where the circuit is constructed using npn transistors has been particularly described here, the above concept can also be applied to the case where the circuit is constructed using pnp transistors.
以上説明したように、本発明による論理回路は回路構成
素子数が少ないので、特に集積回路に使用すれば集積密
度が向上するので有効である。As explained above, since the logic circuit according to the present invention has a small number of circuit components, it is particularly effective when used in an integrated circuit because it improves the integration density.
第1図は従来の論理回路の一例の回路図、第2図は本発
明の実施例を示す。
A1.A2.A3.A4.A5.A6.A7・・・・・
・信号入力端子、X・・・・・・信号出力端子、Ll、
L2.L3゜”4 t ”5 、”6 、”7 、N1
□、N12.N13.N14゜N2□、N2□、N23
・・・・・・信号入力線、M12M2゜M3.M4.M
5.M6.N31°°・・・・信号出力線、Trl 。
Tr2 ・・・・・・トランジスタ。FIG. 1 is a circuit diagram of an example of a conventional logic circuit, and FIG. 2 shows an embodiment of the present invention. A1. A2. A3. A4. A5. A6. A7...
・Signal input terminal, X...Signal output terminal, Ll,
L2. L3゜”4t”5,”6,”7,N1
□, N12. N13. N14゜N2□, N2□, N23
...Signal input line, M12M2゜M3. M4. M
5. M6. N31°°...Signal output line, Trl. Tr2...Transistor.
Claims (1)
1個以上のエミッタを有するトランジスタ群とを具備し
、前記第1信号入力線と前記トランジスタのベースとを
1対lに結合し、前記第2信号入力線を前記トランジス
タのエミッタに結合し、該トランジスタのコレクタを、
前記信号出力線に共通結合して出力信号を取り出すこと
を特徴とする論理回路。1 first and second signal input line groups, a signal output line,
a transistor group having one or more emitters, the first signal input line and the bases of the transistors are coupled in a one-to-l ratio, the second signal input line is coupled to the emitters of the transistors; the collector of the transistor,
A logic circuit characterized in that it is commonly coupled to the signal output line and outputs an output signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6806178A JPS5833729B2 (en) | 1978-06-06 | 1978-06-06 | logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6806178A JPS5833729B2 (en) | 1978-06-06 | 1978-06-06 | logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54158852A JPS54158852A (en) | 1979-12-15 |
JPS5833729B2 true JPS5833729B2 (en) | 1983-07-21 |
Family
ID=13362884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6806178A Expired JPS5833729B2 (en) | 1978-06-06 | 1978-06-06 | logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5833729B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0343372Y2 (en) * | 1984-05-23 | 1991-09-11 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1204171A (en) * | 1983-07-15 | 1986-05-06 | Stephen K. Sunter | Programmable logic array |
-
1978
- 1978-06-06 JP JP6806178A patent/JPS5833729B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0343372Y2 (en) * | 1984-05-23 | 1991-09-11 |
Also Published As
Publication number | Publication date |
---|---|
JPS54158852A (en) | 1979-12-15 |
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