JPH0241867Y2 - - Google Patents

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Publication number
JPH0241867Y2
JPH0241867Y2 JP1981000874U JP87481U JPH0241867Y2 JP H0241867 Y2 JPH0241867 Y2 JP H0241867Y2 JP 1981000874 U JP1981000874 U JP 1981000874U JP 87481 U JP87481 U JP 87481U JP H0241867 Y2 JPH0241867 Y2 JP H0241867Y2
Authority
JP
Japan
Prior art keywords
circuit
emitter follower
integrated circuit
external connection
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981000874U
Other languages
Japanese (ja)
Other versions
JPS57115257U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981000874U priority Critical patent/JPH0241867Y2/ja
Publication of JPS57115257U publication Critical patent/JPS57115257U/ja
Application granted granted Critical
Publication of JPH0241867Y2 publication Critical patent/JPH0241867Y2/ja
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案はエミツタホロワ出力回路を有する集積
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit having an emitter follower output circuit.

集積回路で最も高速動作が可能なECL型集積
回路は、増々複雑化、高性能化する装置にその需
要が拡大しつつある。ECL型集積回路の基本回
路は第1図に示すように、定流電源1に各エミツ
タが接続され、コレクタには抵抗6,7が接続さ
れたトランジスタ2,3,4で構成される電流切
換回路の出力にエミツタホロワ−トランジスタ5
のベースを接続し、そのエミツタを集積回路の外
部接続用端子8を介して外部負荷に加えている。
この時外部負荷が容量性負荷であつてもエミツタ
ホロワ−トランジスタ5の低駆動インピーダンス
により、高速に充電を行なわしめるため極めて高
速のスイツチングが可能となる特長を持つてい
る。また、複数のエミツタホロワ−出力回路のエ
ミツタを共通接続するだけで論理動作を行なわし
めるいわゆるワイヤードOR接続も可能であるた
め、論理段数の低減にも有効である。
Demand for ECL integrated circuits, which are capable of operating at the highest speed among integrated circuits, is expanding in equipment that is becoming increasingly complex and sophisticated. As shown in Figure 1, the basic circuit of the ECL type integrated circuit is a current switching circuit consisting of transistors 2, 3, and 4, each emitter connected to a constant current power source 1, and resistors 6 and 7 connected to the collector. Emitter follower transistor 5 at the output of the circuit
, and its emitter is applied to an external load via an external connection terminal 8 of the integrated circuit.
At this time, even if the external load is a capacitive load, the low driving impedance of the emitter follower transistor 5 allows charging to be performed at high speed, so that extremely high-speed switching is possible. Furthermore, a so-called wired OR connection in which a logic operation is performed by simply connecting the emitters of a plurality of emitter follower output circuits in common is also possible, which is effective in reducing the number of logic stages.

このような特長を持つECL型集積回路は従来、
エミツタホロワ出力回路であるトランジスタ5の
エミツタは直接外部接続用端子8に接続されて、
抵抗で終端されることなくチツプ外に引き出され
ている。終端抵抗は、外部接続用端子8に接続さ
れる信号伝播ラインのインピーダンスに合つた抵
抗値をもつた個別抵抗が集積回路の外で接続され
るのが一般的であつた。しかし、この構成ではエ
ミツタホロワ出力回路の数が多くなると、必要と
される個別抵抗が多く、外付素子数を抵減できな
いという欠点があつた。
Conventionally, ECL type integrated circuits with these features were
The emitter of the transistor 5, which is the emitter follower output circuit, is directly connected to the external connection terminal 8.
It is led out of the chip without being terminated with a resistor. As the terminating resistor, an individual resistor having a resistance value matching the impedance of the signal propagation line connected to the external connection terminal 8 was generally connected outside the integrated circuit. However, this configuration has the disadvantage that when the number of emitter follower output circuits increases, a large number of individual resistors are required, and the number of external elements cannot be reduced.

この問題に対し、エミツタホロワトランジスタ
5のエミツタに終端抵抗を集積回路チツプ上で接
続しておくことも実験的には検討されたが、この
場合、出力信号を受ける回路の信号入力部では信
号源インピーダンスが信号伝播ラインのインピー
ダンスのために高インピーダンスとなるため、信
号伝播ラインがやや長くなると、信号反射を引き
起し、高速動作ができなくなる欠点があつた。ま
た、終端抵抗を集積回路チツプ上で接続したエミ
ツタホロワ出力回路を用いた場合には、前述のワ
イヤードOR接続を実施する場合、終端抵抗がワ
イヤードOR接続されるエミツタホロワ出力回路
の数だけ並列接続されることになるため、その終
端インピーダンスが下りすぎ、エミツタホロワ出
力回路の出力駆動能力を大巾に高めておかないと
実際上ワイヤードOR接続が不可能となるなどの
欠点があつた。
To solve this problem, it has been experimentally considered to connect a termination resistor to the emitter of the emitter follower transistor 5 on the integrated circuit chip, but in this case, the signal input section of the circuit that receives the output signal is Since the signal source impedance becomes high impedance due to the impedance of the signal propagation line, if the signal propagation line becomes somewhat long, signal reflection occurs, making high-speed operation impossible. In addition, when using an emitter follower output circuit in which termination resistors are connected on an integrated circuit chip, when implementing the wired OR connection described above, the termination resistors are connected in parallel by the number of emitter follower output circuits to be wired OR connected. As a result, the termination impedance was too low, making wired OR connection practically impossible unless the output drive capability of the emitter follower output circuit was greatly increased.

本考案は、これらの欠点を除き、集積密度の高
い、ワイヤードOR接続の可能な、完全終端可能
な終端方法を実現できるエミツタホロワ出力回路
を有する集積回路を提供するものである。
The present invention eliminates these drawbacks and provides an integrated circuit having an emitter follower output circuit that has a high integration density, enables wired OR connection, and realizes a termination method that allows complete termination.

本考案によれば、終端抵抗は集積回路チツプ内
にエミツタホロワ出力回路とは別に準備され、こ
の終端抵抗の一端は電源端子の一つに、他方はチ
ツプの外部接続用端子に接続されて、他の回路素
子とは電気的に独立した構成の集積回路を得る。
終端抵抗は集積回路チツプ内に準備されているた
め、個別終端抵抗を外部で準備して使用する必要
はなく、従つて実装密度を向上させることができ
る。また、複数のエミツタホロワ出力回路をワイ
ヤードOR接続した時も適当な終端抵抗を選択接
続できるので、終端インピーダンスが下がりすぎ
ることもない。
According to the present invention, a terminating resistor is prepared in the integrated circuit chip separately from the emitter follower output circuit, one end of the terminating resistor is connected to one of the power supply terminals, the other is connected to an external connection terminal of the chip, and the other end is connected to one of the power supply terminals. An integrated circuit having a configuration that is electrically independent from the circuit elements of is obtained.
Since the terminating resistor is provided within the integrated circuit chip, there is no need to prepare and use a separate terminating resistor externally, thereby increasing packaging density. Furthermore, even when multiple emitter follower output circuits are wired OR connected, an appropriate termination resistor can be selected and connected, so the termination impedance will not drop too much.

次に、本考案を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第2図は本考案の一実施例を模式的に示したも
ので、集積回路チツプ10に形成した回路素子を
回路記号で示したものである。外部接続用入力端
子13にトランジスタ21のベースが接続されて
いる。トランジスタ21と22のエミツタは共通
に定電流源16に接続され、かつ各コレクタには
それぞれ負荷抵抗31,32が接続されている。
トランジスタ22のコレクタはトランジスタ23
のベースに接続されている。トランジスタ23と
24のエミツタも共通に定電流源17に接続さ
れ、それらのコレクタにもそれぞれ負荷抵抗3
3,34が接続されている。トランジスタ24の
コレクタはエミツタホロワトランジスタ25に接
続され、そのエミツタは外部接続用出力端子14
にのみ接続されている。トランジスタ26は他の
回路を構成している。終端抵抗35,36は集積
回路チツプ10上で独立して存在しており、これ
ら終端抵抗35,36の各一端は配線を通して電
源(VEE)端子15に接続されている。また、終
端抵抗35の他端は外部接続用端子12に、終端
抵抗36の他端は他の外部接続用端子11に接続
されている。
FIG. 2 schematically shows an embodiment of the present invention, in which circuit elements formed on an integrated circuit chip 10 are shown by circuit symbols. The base of the transistor 21 is connected to the input terminal 13 for external connection. The emitters of the transistors 21 and 22 are commonly connected to the constant current source 16, and the collectors of the transistors 21 and 22 are connected to load resistors 31 and 32, respectively.
The collector of transistor 22 is transistor 23
connected to the base of. The emitters of the transistors 23 and 24 are also commonly connected to the constant current source 17, and their collectors are also each connected to a load resistor 3.
3 and 34 are connected. The collector of the transistor 24 is connected to the emitter follower transistor 25, and its emitter is connected to the output terminal 14 for external connection.
connected only to Transistor 26 constitutes another circuit. Terminating resistors 35 and 36 exist independently on integrated circuit chip 10, and one end of each of these terminating resistors 35 and 36 is connected to power supply (V EE ) terminal 15 through wiring. Further, the other end of the terminating resistor 35 is connected to the external connection terminal 12, and the other end of the terminating resistor 36 is connected to another external connection terminal 11.

エミツタホロワトランジスタ25で形成される
エミツタホロワ出力回路の終端抵抗での終端が必
要な場合には、外部接続用出力端子14に接続さ
れる集積回路に有する終端抵抗(第2図の終端抵
抗35,36に相当するもの)で信号を受信する
回路の直前で信号伝播ラインに一致したインピー
ダンスで終端するようにする。こうすることによ
り、電気的特性上反射をなくすことができる。本
実施例で、エミツタホロワ出力回路からの信号を
外部接続用入力端子13で受ける場合には、外部
接続用入力端子13と外部接続用端子11もしく
は12とを直接接続するようにすれば良い。ま
た、複数のエミツタホロワ出力回路の出力同志を
ワイヤードOR接続して外部接続用入力端子13
で受ける場合も、同様に外部接続用入力端子13
と外部接続用端子11もしくは12とを直接接続
して終端抵抗35もしくは36を接続することに
より容易に実現可能である。
If the emitter follower output circuit formed by the emitter follower transistor 25 needs to be terminated with a terminating resistor, the terminating resistor (the terminating resistor 35 in FIG. , 36) is terminated with an impedance that matches the signal propagation line immediately before the circuit that receives the signal. By doing so, reflection can be eliminated due to electrical characteristics. In this embodiment, when receiving a signal from the emitter follower output circuit at the external connection input terminal 13, the external connection input terminal 13 and the external connection terminal 11 or 12 may be directly connected. In addition, the outputs of a plurality of emitter follower output circuits are wired OR-connected to the input terminal 13 for external connection.
Similarly, when receiving external connection input terminal 13,
This can be easily realized by directly connecting the external connection terminal 11 or 12 and connecting the terminating resistor 35 or 36.

終端抵抗をエミツタホロワトランジスタで構成
されるエミツタホロワ出力回路の出力部分に接続
した従来の構成に比べ、本考案では、エミツタホ
ロワ出力回路には集積回路チツプ10上では前も
つて終端抵抗35,36が接続されていないで、
エミツタホロワ出力回路に接続される信号受信側
で終端抵抗が接続されるので、信号伝播ラインの
インピーダンスによつて受信回路から見た信号源
インピーダンスが高くなり電気的反射を起すよう
なこともない。また、複数のエミツタホロワ出力
回路をワイヤードOR接続しても、終端抵抗が並
列接続されることはなく、従つて終端抵抗の抵抗
値を適当な値にすることができる。エミツタホロ
ワ出力回路の出力の受信回路が複数の場合には、
最遠端にある受信回路を含む集積回路内に準備さ
れた終端抵抗を使用することにより目的を達する
ことが可能である。
Compared to the conventional configuration in which a terminating resistor is connected to the output part of an emitter follower output circuit composed of emitter follower transistors, in the present invention, the emitter follower output circuit is provided with terminating resistors 35 and 36 in advance on the integrated circuit chip 10. is not connected,
Since a terminating resistor is connected on the signal receiving side connected to the emitter follower output circuit, there is no possibility that the impedance of the signal propagation line increases the signal source impedance seen from the receiving circuit and causes electrical reflection. Further, even if a plurality of emitter follower output circuits are wired OR-connected, the terminating resistors are not connected in parallel, and therefore the resistance value of the terminating resistor can be set to an appropriate value. If there are multiple receiving circuits for the output of the Emitsuta follower output circuit,
This can be achieved by using a termination resistor provided in the integrated circuit containing the receiving circuit at the farthest end.

以上の説明から明らかなように本考案によれ
ば、実装密度が高く、ワイヤードオア接続が可能
で、良好な電気的特性を実現可能なエミツタホロ
ワ出力回路を有する集積回路を提供できるもの
で、その実用的な有効性は極めて高いものであ
る。
As is clear from the above explanation, according to the present invention, it is possible to provide an integrated circuit having an emitter follower output circuit that has a high packaging density, enables wired-OR connection, and can realize good electrical characteristics, and can be used in practical applications. Its effectiveness is extremely high.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のECL型集積回路を示す回路図、
第2図は本考案による一実施例を示す図である。 1,16,17……定電流源、10……集積回
路チツプ、2,3,4,5,21,22,23,
24,25,……トランジスタ、6,7,31,
32,33,34……抵抗、35,36……終端
抵抗、8,11,12……外部接続用端子、13
……外部接続用入力端子、14……外部接続用出
力端子、15……電源端子。
Figure 1 is a circuit diagram showing a conventional ECL type integrated circuit.
FIG. 2 is a diagram showing an embodiment of the present invention. 1, 16, 17... constant current source, 10... integrated circuit chip, 2, 3, 4, 5, 21, 22, 23,
24, 25, ...transistor, 6, 7, 31,
32, 33, 34... Resistor, 35, 36... Terminating resistor, 8, 11, 12... External connection terminal, 13
... Input terminal for external connection, 14 ... Output terminal for external connection, 15 ... Power supply terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路チツプ上にエミツタが直接外部接続用
端子の1つに接続されたトランジスタで構成され
るエミツタホロワ出力回路と他の回路素子とは電
気的に独立した複数個の抵抗とを含み、該抵抗の
それぞれの一方の端子は電源端子の一つに接続
し、他方の端子は該集積回路チツプ上に形成され
た他の外部接続用端子の各1つにそれぞれ接続さ
れていることを特徴とする集積回路。
The integrated circuit chip includes an emitter follower output circuit consisting of a transistor whose emitter is directly connected to one of the external connection terminals, and a plurality of resistors that are electrically independent from other circuit elements. An integrated circuit characterized in that one terminal of each is connected to one of the power supply terminals, and the other terminal is connected to each one of the other external connection terminals formed on the integrated circuit chip. circuit.
JP1981000874U 1981-01-07 1981-01-07 Expired JPH0241867Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981000874U JPH0241867Y2 (en) 1981-01-07 1981-01-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981000874U JPH0241867Y2 (en) 1981-01-07 1981-01-07

Publications (2)

Publication Number Publication Date
JPS57115257U JPS57115257U (en) 1982-07-16
JPH0241867Y2 true JPH0241867Y2 (en) 1990-11-08

Family

ID=29799413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981000874U Expired JPH0241867Y2 (en) 1981-01-07 1981-01-07

Country Status (1)

Country Link
JP (1) JPH0241867Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165670A (en) * 1979-06-12 1980-12-24 Toshiba Corp Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5476677U (en) * 1977-11-11 1979-05-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165670A (en) * 1979-06-12 1980-12-24 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPS57115257U (en) 1982-07-16

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