JP2672969B2 - ECL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding an ECL circuit for a master slice LSI, it is possible to realize a three-valued logic without saturating a transistor simply by changing the connection of the ECL circuit for an existing master slice LSI. For the purpose, the first resistor for level shift and the second resistor for current switch
In a master slice LSI circuit composed of a plurality of gates consisting of an ECL circuit including the resistance of a circuit as a circuit element, a transistor is added in parallel to the reference side transistor of the gate consisting of a level shift type ECL circuit. A gate composed of a non-level shift type ECL circuit to be driven is provided, and the collector circuit of the output side transistor of the ECL circuit which constitutes this gate is composed of the first resistor and the second resistor connected in series. To configure.

[Industrial applications]

The present invention relates to an ECL circuit, particularly an ECL circuit for a master slice LSI.

[Conventional technology]

ECL (Emitter C
oupled Logic) circuit is used.

FIG. 5 is a diagram showing an example of a conventional level shift type ECL circuit.

In Figure 5, Tr ₁ , Tr ₂ , Tr ₃ and Tr ₄ are input transistors, Tr ₅ is a reference transistor, R ₀ is a level shift resistor, R
_CS1 and R _CS2 are current switch resistances, Tr ₆ and Tr ₇ are transistors for extracting the output by the emitter follower, and R _EF
Is a terminating resistance, i _CS is a constant current circuit, V _BB is a reference voltage, V _EE is a current switch voltage, and V _TT is a terminating voltage.

 The operation of the conventional example shown in FIG. 5 will be described below.

When the input transistor Tr _1, Tr _2, Tr ₃ and "1" to any one of Tr ₄ is input, the transistor is ON, the reference transistor Tr ₅ is turned OFF. As a result, the collector potential of the reference transistor Tr ₅ rises, and the “1” level output whose potential has dropped by the amount of the base-emitter ON potential drop of Tr ₆ is output to the OR output.

The output of Tr ₆ is the input transistors Tr ₁ , Tr ₂ , Tr ₃ and Tr ₄
When "1" is input to any one of them, it becomes "1", so it is an OR output.

On the other hand, Tr ₇ operates in the opposite way to Tr ₆ . That is, one of the input transistors Tr ₁ , Tr ₂ , Tr ₃ and Tr ₄
"1" is input to One, because the transistor is turned ON, the collector potential drops, the output NOR, based Tr ₇ from the collector potential - emitter ON voltage component, dropped potentials "0 "The level output potential is output.

The output of Tr ₇ is the input transistors Tr ₁ , Tr ₂ , Tr ₃ and Tr ₄
When "1" is input to any one of them, it becomes "0", so it is NOR output.

 FIG. 6 is an equivalent circuit of the conventional example shown in FIG.

As can be seen from Fig. 6, the circuit of Fig. 5 has four inputs.
It has an OR output and a NOR output for IN ₁ , IN ₂ , IN ₃ and IN ₄ . This relationship can be expressed as follows.

OR = IN ₁ + IN ₂ + IN ₃ + IN ₄ NOR = ▲ ▼ By the way, in order to speed up the circuit of FIG. 5, it is necessary to reduce the logic amplitude. This is because the delay time due to the parasitic capacitance shown as C in Fig. 5 (about 0.7R _CS × C) by reducing the current switch resistances R _CS1 and R _CS2 .
Can be realized by reducing.

Also, when the logic amplitude inside the LSI is made smaller than the logic amplitude outside the LSI, it is necessary to perform level shift in order to obtain the consistency of the reference level. This is done by the level shift resistor R ₀ . In the case of FIG. 5, the level shift is
Only ΔV = R ₀ × i _{CS is} performed.

FIG. 7 is a diagram showing logic levels of the conventional ECL circuit shown in FIG.

As can be seen from FIG. 7, the logic amplitude outside the LSI is made larger than the logic amplitude inside the LSI. The reason for this is LSI
This is because the noise factor due to temperature difference and the like is large because the signal is transmitted to the outside of the device to other elements, and accordingly, it is necessary to increase the logic amplitude to increase the transmission margin.

Further, it can be seen from FIG. 7 that the consistency between the external level and the internal level is poor without the level shift resistor R ₀ .

[Problems to be solved by the invention]

The conventional ECL circuit for master slice LSI had a problem that it could not realize ternary logic.

It is an object of the present invention to provide an ECL circuit that can realize a three-valued logic without saturating a transistor simply by changing the connection of an existing ECL circuit for a master slice LSI.

[Means for solving the problem]

In order to achieve the above object, the ECL circuit of the present invention comprises:
In a master slice LSI circuit composed of a plurality of gates composed of an ECL circuit including a first resistance for level shift and a second resistance for current switch as circuit elements, a gate composed of a level shift type ECL circuit A transistor is added in parallel to the reference side transistor of, and a gate composed of a non-level shift type ECL circuit for driving this transistor is provided, and the collector circuit of the output side transistor of the ECL circuit which constitutes this gate is The resistor and the second resistor are configured to be connected in series.

[Action]

In the ECL circuit of the present invention, a transistor is added in parallel to the reference side transistor of the gate formed of the level shift type ECL circuit, and the gate formed of the non-level shift type ECL circuit for driving this transistor is provided. The collector circuit of the output-side transistor of the ECL circuit that constitutes this gate consists of the level shift resistance of the level shift type ECL circuit and the current switch resistance connected in series.

Therefore, the logic level for driving the transistor connected in parallel to the reference side transistor of the gate composed of the level shift type ECL circuit is the level shift type EC.
It becomes higher than the logic level of the plurality of input transistors and the reference side transistor of the L circuit.

As a result, the transistor connected in parallel to the gate reference side transistor formed of the level shift type ECL circuit can be turned on regardless of the states of the plurality of input transistors of the level shift type ECL circuit.

As described above, according to the ECL circuit of the present invention, in addition to the OR output and NOR output by the plurality of input transistors of the level shift type ECL circuit, the level shift type ECL circuit
The output is obtained by the transistor connected in parallel to the reference side transistor of the gate of the circuit. That is, 3
Value logic can be realized.

〔Example〕

 FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, Tr ₁ , Tr ₄ , Tr ₇ , Tr ₈ , Tr ₁₃ and Tr ₁₄ are input transistors, Tr ₂ , Tr ₅ , Tr ₉ and Tr ₁₅ are reference transistors, R ₀ is a level shift resistor, R _CS1 And R _CS2 is the current switch resistance, Tr ₁₀ is the transistor added in parallel to the reference Tr ₉ , Tr
₁₆ is a transistor added in parallel to the reference Tr ₁₅ , Tr ₃ , Tr ₆ , and T
r ₁₁ , Tr ₁₂ and Tr ₁₇ are transistors for extracting the output by an emitter follower, R _EF is a termination resistor, V _BB is a reference voltage, V _EE is a current switch voltage, V _TT is a termination voltage, and A is a gate 1 Input, B is input of gate 2, C is output of gate 2 and input of gate 3, D is input of gate 3, E is gate 3
Output, F is output of gate 3, G and H are inputs of gate 4, X
Is the output of gate 1 and Y and Y'are the outputs of gate 4.

Hereinafter, the present embodiment will be described focusing on the level shift type ECL circuit which constitutes the gate 3.

The level shift type ECL circuit that constitutes the gate 3 is added in parallel to the input transistors Tr ₇ and Tr ₈ , the reference transistor Tr ₉ , the level shift resistor R ₀ , the current switch resistors R _CS1 and R _CS2 , and the reference transistor Tr _9. The transistor Tr ₁₀ , the transistor Tr ₁₁ for taking out the OR output on the output side by the emitter follower, the transistor Tr ₁₂ for taking out the NOR output on the input side by the emitter follower, and the terminating resistor R _EF .

The transistor Tr ₁₀ added in parallel to the reference transistor Tr ₉ is driven by the output of the gate 1.

The gate 1 is composed of a non-level shift type ECL circuit, and has an input transistor Tr ₁ , a reference transistor Tr ₂ , a level shift resistance R ₀ , a current switch resistance R _CS2 , and a transistor Tr ₃ for taking out an OR output on the output side by an emitter follower. , Terminating resistance R _EF .

Of the input transistors Tr ₇ and Tr ₈ of the level shift type ECL circuit forming the gate 3, the output C of the gate 2 is applied to Tr _7, and the gate having the same logic output level as that of the gate 2 is applied to Tr _8. The input D driven by is applied. The transistor Tr ₁₀ added in parallel with the reference transistor Tr ₉ is driven by the output X of the gate 1.

As a result, the OR output E of the inputs C and D is output from the Tr ₁₁ , and the NOR output F of the inputs C and D is output from the Tr ₁₂ . Also, when A = “1” is input to the gate 1,
Gate 1 outputs X = "1" and Tr ₁₀ is turned on, so Tr ₁₁ to E = "0" regardless of the state of inputs C and D.
Is output and Tr ₁₂ outputs F = “1”.

FIG. 2 is a diagram showing a partial equivalent circuit centered on the gate 3 of the circuit of FIG. FIG. 3 is a logic diagram of the circuit shown in FIG.

FIG. 4 is a diagram showing logic levels of the circuit of FIG.

As can be seen from FIG. 4, the V _OH of the outputs X and Y are sufficiently higher than the outputs C and E of the level shift type ECL circuit, and the V _OL of the outputs X and Y are the outputs C and E. It is about the same.

To make V _OH of the outputs X and Y sufficiently higher than the outputs C and E of the level shift type ECL circuit, the gate 3
Transistor Tr ₁₀ added to the reference transistor Tr ₉ and the transistor added to the reference transistor Tr ₁₅ of the gate 4
It is necessary to realize three-valued logic by Tr ₁₆ , and it is necessary to make V _OL of outputs X and Y almost the same as that of outputs C and E by using transistor Tr ₁₀ and gate transistor 3 added to reference transistor Tr _9. It is necessary to prevent the transistor Tr ₁₆ added to the reference transistor Tr ₁₅ of the gate 4 from being saturated.

Low V _OH levels of outputs C and E are applied to A, B, C, D, G and H, and added to transistor Tr ₁₀ added to reference transistor Tr ₉ of gate 3 and reference transistor Tr ₁₅ of gate 4. The transistor Tr ₁₆ has a high V _{OH of} output X and Y.
Apply level.

The emitter follower resistance of the gate 4 is composed of two series resistors R _EF1 and R _EF2 . This is a means for producing the same V _OH level in the gate 1 and the gate 4 formed of the non-level shift type ECL circuit as the gate 2 and the gate 3 formed of the level shift type ECL circuit.

Here, a case where saturation occurs in the transistor will be described.

Saturation of the transistor occurs when the V _OL level is too low when a high V _OH level such as the output X of the gate 1 is input to the transistor Tr ₁₆ added to the reference transistor Tr ₁₅ of the gate 4.

That is, when it is attempted to generate V _OL at the output Y which is as low as the external level, V _X of the gate 4 becomes almost equal to the output X of the gate 1 even in the normal state, and LS due to R _GND
Due to the voltage drop of the I power supply and the voltage drop due to the collector resistance in the transistor, the base-collector junction of Tr ₁₆ becomes forward biased and saturation occurs. In high-density LSI, the miniaturization transistor is used, so the collector resistance is particularly large, so saturation easily occurs.

In this embodiment, in order to prevent saturation of the transistor, V _OL output X and Y are set to be the substantially the same as the output C and E.

〔The invention's effect〕

According to the ECL circuit of the present invention, ternary logic can be realized without saturating the transistor simply by changing the connection of the ECL circuit for the existing master slice LSI.

[Brief description of the drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a partial equivalent circuit of the circuit of FIG. 1, FIG. 3 is a logic diagram of the circuit of FIG. 2, and FIG. 4 is FIG. 5 is a diagram showing a logic level of the circuit of FIG. 5, FIG. 5 is a diagram showing a conventional example, FIG. 6 is a diagram showing an equivalent circuit of the conventional example, and FIG. 7 is a diagram showing a logic level of the conventional example. In Figure 1, Tr ₁ , Tr ₄ , Tr ₇ , Tr ₈ , Tr ₁₃ , Tr ₁₄ : Input transistors Tr ₂ , Tr ₅ , Tr ₉ , Tr ₁₅ : Reference transistors R ₀ : Level shift resistors R _CS1 , R _CS2 : Current switch resistance Tr ₁₀ : Transistor added in parallel with reference Tr ₉ Tr ₁₆ : Transistor added in parallel with reference Tr ₁₅ Tr ₃ , Tr ₆ , Tr ₁₁ , Tr ₁₂ , Tr ₁₇ : For extracting output by emitter follower Transistor R _EF : Termination resistance V _BB : Reference voltage V _EE : Current switch voltage V _TT : Termination voltage A: Gate 1 input B: Gate 2 input C: Gate 2 output and gate 3 input D: Input of gate 3 E: Output of gate 3 F: Output of gate 3 G, H: Input of gate 4 X: Output of gate 1 Y, Y ': Output of gate 4

Claims (1)

(57) [Claims] 1. A plurality of gates composed of an ECL circuit including a first resistance (R ₀ ) for level shift and a second resistance (R _CS1 , R _CS2 ) for current switch as circuit elements. In the master slice LSI circuit, the gate consists of a level shift type ECL circuit (gate 3)
In parallel with the reference side transistor (Tr ₉ ) of the transistor (T
r ₁₀ ) is added, and a gate (gate 1) consisting of a non-level shift type ECL circuit that drives this transistor (Tr ₁₀ ) is provided, and the output side transistor (Tr 1) of the ECL circuit that constitutes this gate (gate 1) is provided. The collector circuit of ₂ ) is an ECL circuit characterized by comprising the first resistor (R ₀ ) and the second resistor (R _CS2 ) connected in series.