JPH052439A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption and also to reduce the skew of a clock signal for a semiconductor integrated circuit which distributes the clock signals. CONSTITUTION:The clock signal supplied from a precedent stage device is inputted to an input terminal 4 via a precedent stage device output transistor TR 2 and then terminated at a terminating potential VT via a signal wiring 7, a resistance terminating terminal 5, and a terminating resistor 3. If an emitter- coupled logic ECL circuit is taken as an example of a clock signal level, the resistor 3 is set at 50OMEGA with the terminating potential VT set at -2V in general respectively. Under such conditions, a large current of about 15mA flows to the TR 2 on an average and this current value is transmitted through the inside of a chip 1 via a signal wiring 7. Then each load circuit included in a semiconductor integrated circuit is driven by four signal wirings 8 branched out of the wiring 7 respectively. Thus the clock input signals can be distributed into the semiconductor integrated circuit with the small skew. In addition, a signal current passes through the inside of the chip 1 from the TR 2 and is terminated by the resistor 3 outside the chip 1 and therefore no power is consumed inside the chip 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit with a clock signal distribution function that requires signal input using a terminating resistor.

[0002]

2. Description of the Related Art In recent years, it has become important to transmit a clock input signal over a wide range of a semiconductor integrated circuit chip with a small skew as the integration and speed of a semiconductor integrated circuit increase. ..

In a conventional semiconductor integrated circuit for this purpose, as shown in FIG. 4, a plurality of clock drivers 6 having a high load driving capability are arranged inside a chip 1 of the semiconductor integrated circuit. Then, by connecting between the corresponding clock drivers 6 by the signal wirings 8 and 9 and the like whose wiring lengths are predetermined, the same clock signal skew inside the chip 1 of the semiconductor integrated circuit can be reduced. It is generally suppressed to.

Here, the clock signal input to the chip 1 of the semiconductor integrated circuit from the preceding device is
It is input to the input terminal 4 via the front device output transistor 2 and the terminating resistor 3, and then input to the clock driver 6 arranged inside the chip 1.

[0005]

In the above-described conventional semiconductor integrated circuit with a clock signal distribution function, in order to reduce the clock signal skew, a clock driver having a high load driving capability, that is, a large power consumption, is used in the semiconductor. It is necessary to arrange a large number of chips in the chip of the integrated circuit, which has a drawback that the power consumption of the entire semiconductor integrated circuit significantly increases.

[0006]

A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a function of inputting a clock signal requiring a terminating resistor from an external device and distributing the clock signal in a semiconductor chip, A signal input terminal provided on the semiconductor chip as an input terminal of the clock signal, and a resistance termination terminal provided on the semiconductor chip as an output terminal of the clock signal, which is connected to a predetermined terminating resistor, and the signal input terminal. At least a signal wiring that connects the resistance termination terminal in a state of penetrating the semiconductor chip is configured.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a main structure of a chip of a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the input terminal 4, the resistance termination terminal 5, the four clock drivers 6, and these clock drivers 6 are connected in correspondence with the preceding stage device output transistor 2. The chip 1 including the signal wirings 7 to 9 and the terminating resistor 3 connected to the resistor terminating terminal 5 are provided.

The clock signal output from the preceding stage device is input to the input terminal 4 via the preceding stage device output transistor 2, and passes through the signal line 7, the resistance termination terminal 5 and the termination resistor 3 at the termination potential V _T. Terminated.
Considering an ECL (emitter coupled logic) circuit as the clock signal level, the terminating resistor 3 is generally 50Ω and the terminating potential V _T is -2V. In this case, the front device output transistor 2 has an average of about 15
Although a large current of mA flows, this large current value is passed through the inside of the chip 1 by the signal wiring 7 and each of the load circuits in the semiconductor integrated circuit is driven by the four signal wirings 8 branched from the signal wiring 7. As a result, the clock input signal can be distributed within the semiconductor integrated circuit with a small skew, without depending on the arrangement position of the signal wiring 8 branched from the signal wiring 7. Furthermore, in this case, the signal current is transferred from the front device output transistor 2 to the chip 1
There is no power consumption in the chip at this portion because it penetrates through the inside of the chip and is terminated by the terminating resistor 3 outside the chip 1.

In the embodiment shown in FIG. 1, after the signal wiring 7 is branched to the signal wiring 8, a load circuit (not shown) is driven via the clock driver 6 and the signal wiring 9. Signal wiring 7
When the distance between the driven load circuit and the driven load circuit is short, there is no problem in driving the load circuit directly from the signal wiring 8 without the intervention of the clock driver 6, and the clock signal skew can be suppressed to a small level. Needless to say.

Next, FIG. 3 shows a comparison result by a spice simulation of the clock signal skew in the semiconductor integrated circuit according to the present invention and the clock signal skew in the conventional semiconductor integrated circuit. In FIG. 3, the vertical axis represents the clock signal skew (psec),
The horizontal axis represents the length (mm) of the signal wiring for the clock signal in the chip.

In this case, in the conventional example, the clock output signal from the preceding stage device is terminated by the terminating resistor 3 (50Ω) connected to the input terminal 4 through the preceding stage device output transistor 2. It shall be input to the clock driver 6. The output emitter follower current of the clock driver 6 is 1.2 mA as a general value. Further, in the case of the present invention, the clock output signal from the preceding stage device is input to the input terminal 4 via the preceding stage device output transistor 2, and the terminating resistor 3 (50) via the signal wiring 7 and the output terminal 5.
Ω).

Further, the specifications including the dimensions of the signal wirings 8 (see FIG. 4) and 7 (see FIG. 1) in the above conventional example and the present invention are as follows.

[Present Invention] [Conventional Example] Chip length (mm) 10 10 Chip width (μm) 56 2 Chip thickness (μm) 2.6 1 Unit wiring capacitance (pF / mm) 50. 18 Unit wiring resistance (Ω / mm) 0.32 30 As described above, the reason why the signal wiring 7 in the present invention is formed wider and thicker than the signal wiring 8 in the conventional example is that the conventional example. In the load circuit (not shown) connected to the signal line 8 in FIG. 2, only a current of about several μA flows as the base current of the input transistor, whereas the signal wiring 7 of the present invention has been described above. As described above, since a large current of about 15 mA flows, it is a result of considering electro-migration support and potential drop due to wiring resistance. This is for a power supply in a semiconductor integrated circuit. It can be implemented by using a part of the line layer.

Under the above conditions, the average of the rising and falling edges of the signal of the clock signal skew at each position within the length of 10 mm of the signal wirings 7 and 8 is measured at the left end of the signal wirings 7 and 8. The graph shown in FIG. 3 is obtained as a standard. As is clear from FIG. 3, the length of the signal wiring for the clock signal in the chip is 10 mm.
In the case of 1, the clock signal skew of about 300 psec exists in the conventional example, whereas in the present invention, the value is about 40 psec or less, which is extremely small. Further, in the conventional example, the clock driver 6
In the present invention, there is no power consumed in the chip 1 in the portion directly corresponding to the clock signal distribution, while the partial power consumption in the chip 1 is consumed inside the chip 1.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing the main structure of the chip of the second embodiment of the present invention. As shown in FIG. 2, in this embodiment,
A chip 1 including an input terminal 4, three resistance termination terminals 5, and signal wirings 7 to 9 corresponding to the preceding device output transistor 2, and a termination resistor 3 connected to the resistance termination terminal 5.
And is configured.

In FIG. 2, the clock signal from the external device output transistor 2 is input to the signal wiring 7 via the input terminal 4. The signal wiring 7 is branched into three circuits inside the chip 1 and is connected to the terminating resistor 3 via the corresponding resistance terminating terminals 5. In this case, in order to set the impedance viewed from the external preceding stage device output transistor 2 to 50Ω, the values of the terminating resistors 3 connected to the three resistor terminating terminals 5 are set to 150.
Must be set to Ω.

In the second embodiment, as compared with the first embodiment shown in FIG. 1, the length of the signal wiring 9 branched from the signal wiring 7 over a wide range of the chip is set to a shorter value. Since the setting is completed, there is an advantage that the clock signal skew can be reduced in correspondence with a wide range of the chip 1.

[0019]

As described above, according to the present invention, a clock signal input to the input terminal from the outside is directly passed through the inside of the chip by the signal wiring and resistance-terminated via the resistance termination terminal. By branching the clock signal to the load circuit from the wiring, power consumption can be reduced and the clock signal can be branched over a wide range of the inside of the semiconductor integrated circuit with a small skew. ..

[Brief description of drawings]

FIG. 1 is a diagram showing a main configuration of a chip according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a main configuration of a chip according to a second embodiment of the present invention.

FIG. 3 is a comparison diagram of clock signal skew between the present invention and a conventional example.

FIG. 4 is a diagram showing a main configuration of a conventional chip.

[Explanation of symbols]

 1 chip 2 pre-stage device output transistor 3 termination resistor 4 input terminal 5 resistance termination terminal 6 clock driver 7-9 signal wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03H 7/48 C 9184-5J

Claims (1)

1. A semiconductor integrated circuit having a function of inputting a clock signal requiring a terminating resistor from an external device and distributing the clock signal to a semiconductor chip,
A signal input terminal provided on the semiconductor chip as an input terminal of the clock signal, and a resistance termination terminal provided on the semiconductor chip as an output terminal of the clock signal, which is connected to a predetermined terminating resistor, and the signal input terminal. A semiconductor integrated circuit, comprising: at least a signal wiring that connects the resistance termination terminal in a state of penetrating the semiconductor chip.