JPH0580829B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a master slice gate array integrated circuit, and particularly to a cell arrangement of a master slice gate array in emitter coupling logic (hereinafter referred to as ECL). .

(2) Technology background As semiconductor technology advances, high-speed logic circuits are becoming more integrated. The same applies to ECL circuits, and highly integrated ECLIC has been realized.

On the other hand, master slice gate arrays have also been realized in which basic circuits of semiconductor logic circuits, that is, gate circuits, are manufactured in advance and the basic circuits are connected within a semiconductor chip according to the purpose.

Master slice gate arrays require a lot of time to pattern and manufacture the elements that make up the integrated circuit, such as transistors and resistors. A wiring pattern is created and connections are made, that is, each element is wired, when required.
By this method, an IC having the same functions as a custom IC can be realized at low cost.

This master slice gate array is also applied to ECL circuits.

(3) Prior Art and Problems Conventionally, the master slice gate array described above is composed of internal cells (hereinafter referred to as internal cells) and output buffer cells (hereinafter referred to as stopped buffer cells). The internal cells are wired with aluminum wiring or the like within the chip, and the logic desired by the user is configured.

For example, one cell constitutes a flip-flop, a plurality of cells constitutes an adder circuit, and these are further combined to create logic circuits with various functions.

As mentioned above, the internal cell component circuit requires an output buffer to match the logic level with the external circuit. (In some cases, an input buffer may be required for input.) An output buffer cell performs such level conversion. Since the output buffer cell is for level conversion as described above, it has only a single function. Therefore, when a logic result is to be latched and output, a latch function is configured in an internal cell, and the output is output via the output buffer. This method has the problem of using internal cells as output latches, reducing the number of cells that can be used to generate other logic functions.

On the other hand, a terminating resistor is generally connected to an ECL circuit. This is inserted to match the output data when it is input to other ECL circuits etc. via the transmission line.

In other words, the terminating resistance is determined by the transmission line used, and its value is, for example, 25, 50, 100Ω.
etc. have various values. In order to drive these termination resistors, the drive capability of the output buffer of the ECL circuit must be changed in opposition to them. Therefore, in the past, there was a problem in that chips having output buffers corresponding to the terminating resistors had to be prepared in advance.
In other words, there is a limit to the range that can be commonly used by simply changing the conclusion. This resulted in higher costs.

(4) Purpose of the Invention The present invention is intended to solve the above-mentioned problems, and its purpose is to provide an output buffer in which the termination resistance value can be selected by the wiring process and the logic function can be changed by the wiring process. An object of the present invention is to provide an ECL master slice gate array IC having an ECL master slice gate array IC.

(5) Structure of the invention A plurality of internal cells provided in the central region of the chip, a plurality of bonding pads provided in the outer edge region of the chip, and a plurality of bonding pads provided between the internal cells and the bonding pads. , a first output buffer cell having a function of taking the logic of the signal from the internal cell and transmitting the calculation result to the outside of the chip via the bonding pad, and between the internal cell and the bonding pad. a second output buffer cell provided in the chip and having only the function of transmitting a signal from the internal cell to the outside of the chip via the bonding pad; and selecting means for selecting the number of drive transistors connected to the bonding pad.

(6) Examples of the invention Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a cell configuration diagram of an embodiment of the present invention.
An internal cell INT consisting of 10 x 10 cells is placed in the center of chip 1, and 10 output buffer cells OBUF1 are placed on the top and bottom sides of the internal cell INT.
Provide each cell.

In addition, there are output buttons on the left and right sides.
Place OBU2. The signal level of the internal cell INT is different from the external signal level. For example, if the difference between the low level and high level of the external signal is 800mV,
The difference between the low level and high level of the signal level of the internal cell INT is different, such as 600 mV.

Output buffer cell OBUF1 has the same logical function as internal cell INT. For example, one gate has five inputs OR and NOR, and one cell has four gates.

FIG. 2 shows a circuit diagram of the internal cell INT. Transistors T ₁ to T ₅ , resistors R ₁ , R′ ₁ ,
It consists of R ₂ , R′ ₂ , R ₃ , and R ₄ , and a voltage V _BB is applied to the base of the transistor T ₄ and a voltage Vcs is applied to the base of the transistor T ₂ . Further, the power supply Vcc is generally a ground voltage. The power supply V _EE is, for example, -5.2V, and this power supply supplies power for the operation of this circuit.

In the circuit shown in Figure 2, the general ECL
It is an OR/NOR gate circuit in O _OR ,
O _NOR corresponds to OR output and NOR output, respectively.

In the circuit of Fig. 2, input IN is shown as one input, but in the case of multiple inputs, there are multiple transistors similar to transistor _T3 , and the collector and emitter of each transistor are common to transistor _T3. The configuration is connected to the collector and emitter. At this time, the bases of the plurality of transistors serve as the plurality of inputs. Here, resistors R' ₁ and R' ₂ are connected when this gate circuit requires high speed, and are not connected when high speed is not required. This is done through a wiring process.

FIG. 3 is a pattern diagram showing the arrangement of the circuit in FIG. 2 on cells. The aforementioned resistors R' ₁ and R' ₂ are selectively wired during the wiring process.

When resistors R′ ₁ and R′ ₂ are connected, the power consumed by this gate increases, and the speed also increases.

FIG. 4 is another circuit diagram of the internal cell INT. The difference from the circuit of FIG. 2 is that it includes a resistor _R10 . That is, one end of the resistor R ₁ is connected to the collectors of the transistors T ₃ and T ₄ , respectively, and the other end is commonly connected to one end of the resistor R ₁₀ . The other end of resistor _R10 is connected to power supply Vcc.
This resistor _R10 is selectively inserted in the wiring process as described above, and when inserted, the power consumed within this gate decreases, and the speed also decreases.

That is, in FIG. 2, when each gate of the cell in the embodiment of the present invention is required to have high logic operation speed, R' ₁ and R' 2 are added in FIG. 2, and when no speed is required, R' 1 and R' ₂ are added. This should be done during the wiring process so that it is not added.

Similarly, in FIG. 4, when speed is not required, resistor _R10 is inserted, and when speed is required, resistor _R10 is not inserted during the wiring process. This is done to reduce power consumption when speed is not required.

Figure 5 shows the output buffer cell OBUF2.
The circuit diagram of the gate inside is shown. This circuit is the same as the circuit diagram of one gate of the internal cell shown in FIG. 2, except that the resistors R ₃ and R ₄ are removed. At this time, the output O _OR ,
O _NOR outputs to the external circuit and is connected to the bonding pad.

The circuit shown in FIG. 5 has one input, but by connecting a plurality of transistors _T3 , it becomes a multi-input gate, and the circuit in this case corresponds to one gate of the output buffer OBUF1.

That is, the collectors of the plurality of transistors _T3 are connected in common, the emitters are also connected in common, and the bases of the plurality of transistors _T3 serve as inputs. output buffer
The OBUF 1 has a plurality of gate circuits, each of which includes a plurality of transistors _T3 in the circuit shown in FIG. 5 described above. This circuit is similar to the circuit shown in FIG. 2, and is functionally completely the same.

Furthermore, the transistor in the circuit of FIG. 5 is connected to a load resistor, that is, a terminating resistor. This termination resistance is as low as 25Ω, 50Ω, or 100Ω, and if it is 50Ω, the transistor must be able to completely drive it.

FIG. 6 shows a pattern diagram for varying the drive capacitance of the transistors T ₁ and T ₅ that drive the aforementioned termination resistor. Bonding pad PA1 is a terminal to which 50Ω is connected to the outside, and the respective emitters of area H consisting of two transistors are connected by wiring pattern L50. In addition, the bonding pad PA2 is externally
This is a terminal to which 100Ω is connected, and the emitter of one transistor in area H consisting of two transistors is connected by a wiring pattern L100. Although not shown, in the case of 25Ω, for example, four transistors are similarly connected. This connection is determined by the value of the terminating resistor, and the number of connections is selectively determined during the wiring process depending on the value.

All of the embodiments of the present invention use ECL, but this is not limited to ECL, but can also be applied to ICs such as CMOS.

(7) Effects of the Invention As described above, according to the present invention, an ECL master slice gate having an output buffer whose terminating resistance value can be selected by the wiring process and whose logic function can be changed by the wiring process is provided. array
You can get IC. Furthermore, the logic speed and power consumption of internal cells can be selected by the wiring process.

[Brief explanation of the drawing]

FIG. 1 is a cell configuration diagram of an embodiment of the present invention, FIGS. 2 and 4 are internal cell circuit configuration diagrams,
Figure 3 is a wiring pattern diagram of the circuit configuration diagram in Figure 2,
FIG. 5 is a circuit diagram of the output buffer cell, and FIG. 6 is a wiring pattern diagram of the output transistor of the output buffer. 1...chip, INT...internal cell,
OUBF1,2...Output buffer cell,
T ₁ to _{T 5} ...transistor, R ₁ to _{R 4} , R ₁₀ , R′ ₁ ,
R′ ₂ ...Resistance.

Claims (1)

[Claims] 1. A plurality of internal cells provided in the central region of the chip, a plurality of bonding pads provided in the outer edge region of the chip, and a plurality of bonding pads provided between the internal cells and the bonding pads. a first output buffer cell having a function of taking the logic of the signal from the internal cell and transmitting the calculation result to the outside of the chip via the bonding pad; a second output buffer cell provided between the chips and having only the function of transmitting a signal from the internal cells to outside the chip via the bonding pad; and a load connected to the bonding pad from outside the chip. and selecting means for selecting the number of drive transistors connected to the bonding pad accordingly. 2. The integrated circuit device according to claim 1, wherein the internal cell includes a gate having a pair of transistors whose emitters are commonly connected. 3. The plurality of internal cells are arranged within a rectangular area of the chip, the first buffer cell is arranged along a pair of opposite sides of the rectangular area, and the second output buffer cell is arranged along a pair of opposite sides of the rectangular area. 2. The integrated circuit device according to claim 1, wherein the integrated circuit device is arranged along the other pair of sides.